Log inRegister an accountBrowse CSDbHelp & documentationFacts & StatisticsThe forumsAvailable RSS-feeds on CSDbSupport CSDb Commodore 64 Scene Database
You are not logged in 
CSDb User Forums


Forums > C64 Coding > Improved clock-slide
2017-02-28 08:21
lft

Registered: Jul 2007
Posts: 243
Improved clock-slide

If you use timer-based jitter correction, or just VSP, here's a way to shave off one cycle:

http://codebase64.org/doku.php?id=base:improved_clockslide
 
... 16 posts hidden. Click here to view all posts....
 
2017-03-04 09:31
ChristopherJam

Registered: Aug 2004
Posts: 530
FASSEM
2017-03-04 12:21
Copyfault

Registered: Dec 2001
Posts: 195
Woke up this morning with the thought "Ending up on cycle 48 feels odd somehow...". After taking a shower it became clear to me. Scratch that bullshit with the "ends up one cycle earlier...". It's simply wrong! Instead, the clock slide code part must start with a NOP.
;---------------------------------
                 ;23..33
     ldx timer   
                 ;27..37
     lda table,x ;if timer holds the max-val, the table access reads above the page end -> extra cycle!
                 ;32..41
                 ;A=0,0,$ff,1,..,8 (see table)
     sta bra+1   
                 ;36..45
bra  bpl *       
                 ;39 (36+3 for A=0 or 37+2 for A=$ff)
     Nop         ;41
     lda #$a9    ;43
     lda #$a9    ;45
     lda #$a5    ;47
     Nop         ;49
;-------
;pb here
:-------
code ...

table
     !by $08,$07,$06,$05,$04,$03,$02,$01,$ff,$00
;-------------------------------------------------
;page break here
;-------------------------------------------------
     !by $00         

@Frantic: codebase-worthy in this state?
2017-03-06 10:53
ChristopherJam

Registered: Aug 2004
Posts: 530
Yes, all you need is to start and end with NOP.

Kind of wondering about bit shifting approaches now.. For A in 0..3:
  lsr a
  bcs plus1   ;2 or 3 cycles
plus1
  lsr a
  bcs plus2  ;2 or 4 cycles
plus2     ; <- page boundary


..But do you still get the extra cycle cost when branching to the next instruction?
2017-03-06 11:36
HCL

Registered: Feb 2003
Posts: 659
..that's the kind of timing i have seen in some Crest-demos i think. It saves some space, but needs a few more cycles for LSR and an extra branch.
    lsr
    sta br+1
    bcc br
br: bpl..
    nop
    nop
    ..
2017-03-06 11:38
Groepaz

Registered: Dec 2001
Posts: 7931
thats the one posted by hannes sommer in 64er mag about hundred years ago... :=)
2017-03-06 14:41
Ninja

Registered: Jan 2002
Posts: 382
Using page-crossing branches to waste a cycle is not exactly brandnew as well... ;)
2017-03-06 23:52
Copyfault

Registered: Dec 2001
Posts: 195
If I leave out the "Ninja-method" for the moment (which is unbeatable without question) my favourite way of dejittering looks like this:
        lda timer   ;synced to give A=$17,...,$10
        lsr         ;A=$0b,$0b,$0a,$0a,$09,$09,$08,$08, C set for odd values
        bcs .skip1  ;that bit shifting trick found in Crest-demos as mentioned before by HCL
.skip1  asr #$03    ;after "AND #$03": A=$03,$03,$02,$02,$01,$01,$00,$00
                    ;after "LSR": A=$01,$01,$01,$01,$00,$00,$00,$00, C set for odd values
        bcc .skip2  ;waste 2 cycles if C set
        bcs .skip2
.skip4  bne .end    ;waste 4 cycles for non-vanishing A
.skip2  bne .skip4		
.end    
        ...

This is more or less a slightly "stretched" version of the approach found in the Crest-demos. No need for any pb's, even no need for an sbc/eor. It can cope only with eight different delay states, though.

I tried to find a way to get rid of one branch instruction but didn't succeed. Either it's totally trivial and I'm just blind or it is UNpossible :))
2017-03-07 00:13
Copyfault

Registered: Dec 2001
Posts: 195
Quoting ChristopherJam
[...]
Kind of wondering about bit shifting approaches now.. For A in 0..3:
  lsr a
  bcs plus1   ;2 or 3 cycles
plus1
  lsr a
  bcs plus2  ;2 or 4 cycles
plus2     ; <- page boundary

..But do you still get the extra cycle cost when branching to the next instruction?

Iirc you don't get that page-crossing penalty cycle if the branch instruction is at a page end (maybe it was the other way around that you always get it also for a non-taken branch, don't remember correctly anymore). Either way, this
...
lsr
bcs plus2
;---
;pb
;---
plus2

won't work as expected to compensate a two-cycle jitter step.
2017-03-07 06:45
lft

Registered: Jul 2007
Posts: 243
Correct. The offset in the branch instruction is added to the PC, but the PC has already been incremented to the new page so there's no carry and hence no extra cycle.
2017-03-07 07:04
ChristopherJam

Registered: Aug 2004
Posts: 530
Aww, I had a bad feeling about that page crossing. Thanks guys.

I also gather the CIA timers never read zero when they're counting down? (which kills another idea I had..)
Previous - 1 | 2 | 3 - Next
RefreshSubscribe to this thread:

You need to be logged in to post in the forum.

Search the forum:
Search   for   in  
All times are CET.
Search CSDb
Advanced
Users Online
CenTraX/Agony Design
Tao/TRIAD
Almighty God/L64/Ons..
BjørnRøstøen/Panoram..
iAN CooG/HVSC
JAYCE - THE MiNiSTRY
Guests online: 39
Top Demos
1 Uncensored  (9.7)
2 The Shores of Reflec..  (9.7)
3 Edge of Disgrace  (9.7)
4 Coma Light 13  (9.6)
5 Lunatico  (9.6)
6 Comaland 100%  (9.6)
7 Incoherent Nightmare  (9.5)
8 Wonderland XII  (9.5)
9 Comaland  (9.5)
10 Wonderland XIII  (9.5)
Top onefile Demos
1 Dawnfall V1.1  (9.5)
2 Daah, Those Acid Pil..  (9.4)
3 Treu Love [reu]  (9.4)
4 Dawnfall  (9.3)
5 Tunnel Vision  (9.3)
6 One-Der  (9.2)
7 Goatbeard  (9.2)
8 Globe 2016 [reu]  (9.2)
9 Hardware Accelerated..  (9.2)
10 Safe VSP  (9.1)
Top Groups
1 Booze Design  (9.4)
2 Oxyron  (9.4)
3 Censor Design  (9.4)
4 Crest  (9.3)
5 SHAPE  (9.2)
Top Original Suppliers
1 Derbyshire Ram  (9.3)
2 hedning  (9.2)
3 Jazzcat  (9.1)
4 Fungus  (9.0)
5 Irata  (9.0)

Home - Disclaimer
Copyright © No Name 2001-2017
Page generated in: 0.333 sec.