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Forums > C64 Coding > More stable raster problems
2017-04-01 17:16
oziphantom

Registered: Oct 2014
Posts: 478
More stable raster problems

Ok so getting super stable interupts issues ;)

First I did the standard inverted cycle counter 0-8 jitter as on Codebase, but it has a jitter of 0-3 clocks still, which makes it hard to chain the NMIs as each one will jitter and then after 4 of them you are looking at a jitter of 4 - 12 clocks per frame which will then just compound.

So Ninja method to the rescue, super stable to the clock, nice ;) However its uses the following

CIA #1 A
CIA #1 B
CIA #2 A

Which leaves me CIA #2 B, which is annoying. I need an NMI and an IRQ source. The NMI needs to be stable as I need to chain them, but the IRQ just needs to be about every 80 or so clocks, but the NMI needs to "win".

There was a look up opcodes and dynamically make some code to eat clocks, but that needs to trash places spread across the memory map and not really something I can work around I feel.

Any trick I'm missing, some other way to get an IRQ ever so many clocks? Or another way to mitigate the 1-3 jitter on the normal method?
2017-04-01 17:19
chatGPZ

Registered: Dec 2001
Posts: 11088
giving advice will be easier if you'd first tell what exactly you are trying to do. the standard inverted timer thingy shouldnt leave you with 0-3 clocks of jitter, for example :=)
2017-04-01 18:31
Oswald

Registered: Apr 2002
Posts: 5007
debug standard method, then you will have 3 timers left. also a bit sounds like you think if you dejitter one, further nmi's will be flicker free too, which is not the case. dejittering must be done for every individual interrupt.
2017-04-01 23:36
soci

Registered: Sep 2003
Posts: 472
Given the right timing you'll loose NMIs when mixing them with IRQs. Unless the interrupts won't trigger close to each other or the target is a 65C02 or later.

As a workaround you may clear the CIA NMI request independent of the interrupt handler if a "lockup" was detected. This could work if rare glitches are not a big deal, for example while playing digis.
2017-04-02 00:50
ws

Registered: Apr 2012
Posts: 225
I wasn't aware, that the badline would also affect NMI RTI return times, but this little experiment probably visualizes that fact. Yuck!

Thought i'd share.


; CBMPRG Studio Syntax / NMI Return Jitter display // WS^G*P
;------ BASIC - bootloader ---------------------------------

*=$0801
byte $0c,$08,$01,$00,$9e,$20,$32,$30,$36,$32,$00,$00,$00; 0 sys2062 ($080e)

*=$080e

;-----------------------------------------------------------

init cld ; usual nmi irq setup
sei

jsr $e544 ; clear screen

lda #$01
sta $d01a
sta $dc0d

lda #$35 ; gibe le ram
sta $01

lda #$1b ; helps
sta $d011

lda #<irq
sta $FFFE
ldy #>irq
sty $FFFF

lda #$00 ; first interrupt line
sta $d012
lda #$7f
sta $dc0d
lda $dc0d
cli

;-----------------------------------------------------------

idle sta $d020 ; Accumulator is fed by irq
sta $d021
jmp idle

;-----------------------------------------------------------

irq inc $d019 ;neurotypical flag stuff

inc raster+1
raster lda #$00 ;this value is being passed
sta $d012 ;to the idle loop

rti

;-----------------------------------------------------------
;-----------------------------------------------------------
;EOF
2017-04-02 06:12
oziphantom

Registered: Oct 2014
Posts: 478
So Using the code from code base, I was using this code to stabilise an CIA based NMI
         pha
         lda $dc04
         eor #7
         sta *+4
         bpl *+2
         lda #$a9
         lda #$a9
         lda $eaa5
         txa
         pha
         tya
         pha

         ; the rest processes in the IRQ routine

         asl $d019
         pla
         tay
         pla
         tax
         pla
         rti
Where I swapped the asl $d019 for the CIA version. This has a problem in that dc04 can be 8, to which eor #7 gives $f and you end up with a jsr into nomans land.
Luckily on this forum post shortest CIA-stable raster ( which also contains the rest of the codebase code ) Spider-j points out he gets the same thing and offers
 pha
 lda $dd04
 eor #7
 sta *+4
 bpl *+2
 cmp #$c9
 cmp #$c9
 bit $ea24
 bit $ea24
 jmp *+8
 nop
 nop
 jmp *+3
 txa
 pha
 tya
 pha
to which I see a 0-2 cycle jitter on. There was some other code linked in the forum above
clc
adc #$ff-8;A=8-A so result will be 7…0 in A
eor #$ff
sta corr+1 ;self-writing code, the bpl jump-address = A
corr bpl *+2 ;the jump to (A) dependent byte (13 cycles so far)
cmp #$c9 ;A=8->A=0->BPL +2
cmp #$c9 ;
cmp #$c9 ;
cmp $ea ;3 =9 (13+9=22 max delay)
looking at the page it was originaly posted, 6502.org, the writer made this table 
Start Address
$1000    $1001    $1002    $1003    $1004    $1005    $1006    $1007    $1008
-------- -------- -------- -------- -------- -------- -------- -------- --------
cmp #$c9 cmp #$c9 cmp #$c9 cmp #$c9 cmp #$c9 cmp #$c5 cmp $ea  nop
cmp #$c9 cmp #$c9 cmp #$c9 cmp #$c5 cmp $ea  nop     
cmp #$c9 cmp #$c5 cmp $ea  nop
cmp $ea  nop
-------- -------- -------- -------- -------- -------- -------- -------- --------
9        8        7        6        5        4        3        2        0
Cycles
which shows it will also have a 0-2 jitter, to which it did and I got the same results as with Spider-J's code.

My test code was a NMI that did inc d020 dec d020 and the timer value was set to (312*63)-1 on VICE 3.0 X64SC PALC
(312*63) the colour change slid forwards
(312*63)-2 and the colour change slid backwards
The ultimate goal is to have 3~4 "d012 splits" on the screen.
1. opens the border but needs to be on the last cycle of the last line, as having hires bitmap and an open border = black border only
2. closes the border and sets up some other things background colour, multicolour mode, sprites
3. is the optional one, and it restores some sprites after doing a "sprite split" so I can show 4 sprites up top and then 7 below it
4. is a multi to hires split, and a background colour change, however it may have 0,upper 4, lower 4 or 7 sprites overlapping it.
Then there are DIGIS which play every now and then. To which as you can imagine wreck the IRQs badly.
My solution to this is ditch D012 for the "splits" and make them NMIs from a Timer, this way I can set 4 to start on the first clock of the screen ( i.e just past the border) then time out the 40 clocks for the display, then switch to hires. This should make it agnostic to any sprites.

Moving the DIGIs to be IRQ based so the NMIs will take precedent and if a dog bark or bird qwack holds a value for 1 update oh well. However seeing Soci's point oh dear...
2017-04-02 06:38
JackAsser

Registered: Jun 2002
Posts: 1987
It feels that you're building something on a non-solid ground. When stabilizing using timers it's imperative that you have exact control when you start the timer in the first place. As a tip, simply have this in your interrupt handler:

pha
lda $dc04
sta $c000
inc *-1
dec $d019
pla
rti

The run it for a while and inspect $c0xx and make sure the values are in the correct range, i.e. 0-7. Also make sure they're the same range on each run of the code (write run manually to trigger some randomness in your start).

1) So if the range is wrong, then adjust the launch of the timer.
2) If the range differs on each run, then make sure you have a stable IRQ in the code that launches the timer.

When the above is correct you can start replacing the sta $c000 with eor #$07 and do the rest.

Also make sure the stabilization routine, specifically the bpl do NOT cross a page boundary. I.e. have an .align 256 just before the IRQ-handler to mitigate it.
2017-04-02 07:52
oziphantom

Registered: Oct 2014
Posts: 478
So it gives a 1-8 consistantly.
If I switch to an 6526 and use the original code, it works fine. So the issue is I need slide by a clock for 6526 vs 6526A.
2017-04-02 08:05
JackAsser

Registered: Jun 2002
Posts: 1987
Quote: So it gives a 1-8 consistantly.
If I switch to an 6526 and use the original code, it works fine. So the issue is I need slide by a clock for 6526 vs 6526A.


Or don't be so damn optimal. Just do:

sec
lda #$08
sbc $dc04
.
.
.
2017-04-02 10:46
oziphantom

Registered: Oct 2014
Posts: 478
When do I want to load the timer with 8?
When VIC X Cycle & 7 = 0?
2017-04-02 12:32
JackAsser

Registered: Jun 2002
Posts: 1987
Quote: When do I want to load the timer with 8?
When VIC X Cycle & 7 = 0?


With one chip u had 0-7 jitter, with the other 1-8. Taking 8 minus timer value gives you the number of bytes to branch to conpensate. Eor #7 is just an optimized 7-x that's independant of carry state. But since u get 8 also u can't use that optimization and must resort to carry-dependant subtraction.
 
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