| |
oziphantom
Registered: Oct 2014
Posts: 478 |
Force a queded IRQ
Is there a way to pogrammatically ( without the CIAs ) to en-queue an IRQ from within an NMI?
BRK will interrupt an NMI.But is there some other trick, maybe some stack fiddling? |
|
... 21 posts hidden. Click here to view all posts....
|
| |
Bitbreaker
Registered: Oct 2002
Posts: 499 |
Quoting oziphantom
So the ideal path is
Enter NMI
Do stuff
Optionally Queue IRQ
Do other stuff
Exit NMI
IRQ triggers when it can, if queued.
But then it is sufficient to just push the address (+ bogus flags) on the stack to queeue in another task. Then the rti at the end of the NMI handler pulls that stuff form stack again and sets the PC to said address. Then, when th queued irq is also finished with rti, the stuff before entering the nmi is continued. Take care of the registers though and in case also push/pull them from stack.
Other ways are to never acknowledge some irq (lda $dd0d) to make it happen just again and again when you need it, or stop it from happening again by acknowledging. |
| |
TWW
Registered: Jul 2009
Posts: 541 |
Quoting oziphantom
So the ideal path is
Enter NMI
Do stuff
Optionally Queue IRQ
Do other stuff
Exit NMI
IRQ triggers when it can, if queued.
Isn't this normal NMI/IRQ behaviour? Let's say you are playing samples, the sample-player will trigger at the set frequency (by a CIA #2 timer) while any triggered IRQ (typically raster) is executed once the NMI is exited (RTI - clearing the IRQ flag). |
| |
oziphantom
Registered: Oct 2014
Posts: 478 |
Yes that is Standard IRQ behaviour, which is what I'm looking for. I'm pointing out the standard IRQ behaviour to show why you can't just use BBK.
The custom behaviour I'm asking about is "Is there a way to achieve an IRQ in software, such that it behaves in the standard way."
I could push fake status, then address where address is the IRQ routine + bytes to skip its entry, the issues with it is I need to store 2 address ( 1 normal entry and then 1 NMI entry) and possibly set them in multiple places, which could be mitigated by storing my own NMI entry vector and the code look its up Or all IRQs have a fixed length entry and thus the NMI takes IRQ address + constant then store. I could also do read d012 add 2 with care to make sure its not out of range, then set D012 again and enable to interrupt flag, if I had a free CIA IRQ timer I could use it.
However all the balancing acts, double vectors management etc goes away if you can just trick the 6502 into thinking it has a pending IRQ it needs to do. Hence I'm asking to see if there is any way to do such a thing. |
| |
soci
Registered: Sep 2003
Posts: 473 |
I think this is what WF meant:
nmi ;...
bcs do_queued_irq
rti
do_queued_irq jmp ($fffe)
Looks simple to me. But if there's a real IRQ waiting it's not really queued any more. |
| |
TWW
Registered: Jul 2009
Posts: 541 |
The only way to initiate a SW controlled IRQ is by doing a BRK instruction, clearing the I-flag when you know (or have deliberately forced) an IRQ condition or mimic the interrupt handler behaviour (push PC, SR and do a JMP (IRQCODE) which I believe is what WF and Soci is pointing at)
The IRQ line is checked between instructions and as you know trigger the IRQ handler if it is high. The BRK does not pull the line high but triggers the handler anyway (and set's the BRK flag so you have control if the IRQ was launched by a voltage (Cartridge port IRQ line, CIA or VIC) or by SW).
At least this is how I understand it. |
| |
Hein
Registered: Apr 2004
Posts: 933 |
Maybe you want to interrupt an NMI? |
| |
Oswald
Registered: Apr 2002
Posts: 5017 |
I think the issue at hand could be solved with a more sane aproach. |
| |
chatGPZ
Registered: Dec 2001
Posts: 11100 |
Quote:BRK won't force an IRQ
in fact a IRQ will put a BRK into the instruction decoder.... |
| |
soci
Registered: Sep 2003
Posts: 473 |
Quote: Quote:BRK won't force an IRQ
in fact a IRQ will put a BRK into the instruction decoder....
On the schematics it looks like it pulls the data lines low in front of the instruction register to make the next instruction a BRK. Not that it's important ;) |
| |
chatGPZ
Registered: Dec 2001
Posts: 11100 |
lol. yes. (there was some other subtle difference ... i forgot =P) |
| Previous - 1 | 2 | 3 | 4 - Next |
