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Forums > C64 Coding > TIL: The instruction after SEI can be executed before a pending IRQ is handled
2017-11-07 16:56
Krill

Registered: Apr 2002
Posts: 902
TIL: The instruction after SEI can be executed before a pending IRQ is handled

As described here: http://visual6502.org/wiki/index.php?title=6502_Timing_of_Inter..

I never knew this, after all those years, and thought i'd share this as a heads-up.

Thanks to bubis for pointing it out to me!
2017-11-07 17:38
Mixer

Registered: Apr 2008
Posts: 228
Interesting. Any uses for this? Force NMI timing at stable raster? SEI + delay.
2017-11-07 18:54
White Flame

Registered: Sep 2002
Posts: 134
The 6502 implemented delay slots before delay slots were cool. ;-)
2017-11-07 21:39
Oswald

Registered: Apr 2002
Posts: 4124
well it makes sense 6502 have a kind of prefetch. guess hardwired behaviour doesnt wants to drop the instructions before executed.
2017-11-07 22:41
lft

Registered: Jul 2007
Posts: 314
This could lead to horrible bugs indeed, if sei/cli are used around critical sections (like Disable/Enable are often used in AmigaOS).

It's kind of neat that when this happens, the status register gets pushed with the I bit set. That way, RTI will correctly restore an environment in which interrupts are disabled.
2017-11-07 23:05
doynax

Registered: Oct 2004
Posts: 211
Yet an RTI leaving the IRQs unacknowledged does not single-step. Evidently there is either or two cycles of pipelining involved.

I wonder though, is it possible to prove one cycle of latency in the mask register short of cheating with visual6502? Which of the PLP read cycles is the dummy one?

Incidentally this is common a number of architectures and the reason why interrupt barriers exist.
2017-11-08 08:45
ChristopherJam

Registered: Aug 2004
Posts: 682
Wait, so if I understand that correctly if I have
  SEI
  {instruction1}
  {instruction2}

it's possible to get an interrupt *between* instructions one and two?

That could be Bad :(

Thanks for the heads up.
2017-11-08 09:01
JackAsser

Registered: Jun 2002
Posts: 1251
So, always nop after sei? :)
2017-11-08 09:24
ChristopherJam

Registered: Aug 2004
Posts: 682
Eh, anything that doesn't access any memory outside the instruction stream should be fine.

Though if you're being really evil one might have to also remember to avoid using your interrupt handler to modify the instruction immediately following the SEI...
2017-11-08 12:22
Groepaz

Registered: Dec 2001
Posts: 8275
yet another reason to forget this cargo cult of putting sei/cli around raster irq setup :)
2017-11-08 13:54
MagerValp

Registered: Dec 2001
Posts: 891
I think you're reading the trace wrong. The next instruction following an SEI can be fetched, but not executed if an IRQ occurs during the SEI. The instruction will be re-fetched and executed following the RTI.

And yes, protecting IRQ setup with SEI/CLI is still wrong, but not for this reason :)
 
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