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Forums > C64 Coding > TIL: The instruction after SEI can be executed before a pending IRQ is handled
2017-11-07 16:56
Krill

Registered: Apr 2002
Posts: 902
TIL: The instruction after SEI can be executed before a pending IRQ is handled

As described here: http://visual6502.org/wiki/index.php?title=6502_Timing_of_Inter..

I never knew this, after all those years, and thought i'd share this as a heads-up.

Thanks to bubis for pointing it out to me!
 
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2017-11-12 14:47
Groepaz

Registered: Dec 2001
Posts: 8275
Quote:
yeah, until you dont and start having bugs, which is always the case.

i know its useless to explain, but: mindlessly doing sei/cli and not thinking about when to do it and how to enable/disable the interrupts and their sources is what creates the bugs, not omitting it and knowing what to do. as a matter of fact, that kind of nonsense gave me a lot of headache in a certain demo i linked from parts made by a coder with the same mindset - and the whole "trick" to make it work flawless and bugfree was removing this sei/cli style interrupt setups and move them where they belong - and when they happen at the right time there is simply no need for sei/cli anymore (granted, it doesnt hurt either. however still doing it equals writing 0 to $d020 at random places, just to be sure the border is still black).
2017-11-12 14:58
Krill

Registered: Apr 2002
Posts: 902
Quoting Groepaz
writing 0 to $d020 at random places, just to be sure the border is still black
Which then produces grey dots all over the place on many VICs, another pet peeve of mine! :)
2017-11-12 15:08
Oswald

Registered: Apr 2002
Posts: 4126
Groppie, except your bugs werent caused by the sei/cli pair, but the irq setup wasnt timed correctly. and the bugs could have been even worse if those irq inits were interrupted by the raster irqs.
2017-11-12 16:14
Groepaz

Registered: Dec 2001
Posts: 8275
again, let me write it in bold for you:

IF the IRQ setup had been timed correctly THEN SEI/CLI would not have been required. and Blindlessly using SEI/CLI made it "work" WITH THE BUGS.

and sure, without SEI/CLI the broken setup might have not worked at all. i totally prefer this over halfassed buggy glitchfest however.
2017-11-12 17:20
Oswald

Registered: Apr 2002
Posts: 4126
"without SEI/CLI the broken setup might have not worked at all."

thank you.
2017-11-12 18:06
Krill

Registered: Apr 2002
Posts: 902
It's not uncommon that bugs cause erroneous behaviour only in the presence of other bugs. Fix only either, and the other lies dormant until some later time, fix both and you win. :)
2017-11-12 18:25
Groepaz

Registered: Dec 2001
Posts: 8275
indeed, that sei/cli stuff only masked other - and bigger - problems.
2017-11-12 19:11
Oswald

Registered: Apr 2002
Posts: 4126
Quote: It's not uncommon that bugs cause erroneous behaviour only in the presence of other bugs. Fix only either, and the other lies dormant until some later time, fix both and you win. :)

sei/cli wasnt there to fix a bug.
2017-11-12 19:29
Groepaz

Registered: Dec 2001
Posts: 8275
time for some classic rock
2017-11-13 00:02
Copyfault

Registered: Dec 2001
Posts: 216
Quoting Krill
Hmm, what does that setup from timer IRQ save? I don't see the shortening (and you'd also have to ack the IRQ yourself). :)
Ah, you're right with that acknowledging of the IRQ which would come "on top".

Quoting Krill
And please explain your notion of "irq-levels". How many are there? Are interrupt handlers themselves interrupted? Are there more banking settings than all-RAM ($30/$34) for main loop and with IO ($35) for interrupt handlers? Something going via $0314/15?
Yes, what did I mean with "irq-level" *questioningmyself*? I just wanted to distinguish between a "level=0" situation which would be code running outside any irq (which usually is the main loop) and a "level>0" situation for code running inside an IRQ. As there is a certain priority among the different IRQ triggers (e.g. NMI beats Raster), one could define the "irq-level" along these priorities; alternatively, an irq-level could also describe the "depth" of the IRQ trigger chain which occurs when an IRQ is triggered on code running inside an IRQ and so on, but...

...but for the case I had in mind, the terms "main loop" and "inside Raster IRQ" suffice, so I better switch to these now. Usually, I have a main loop running and a raster irq set up. I want a clear separation between the memory access: full ram ($01=$34) in the main loop and IO ($01=$35) in the irq code. As there are usually some IO-registers to be initialised during init, I at least need $01=$35 once in the main loop. By misusing the CIA1-irq as stated in one of my former postings I could avoid this and have all IO accesses inside the IRQ.

Which leaves me with a little question. Is it possible to have an IRQ execution directly after the write cycle of that STA $D019?
...
sta $d019
-> irq possible _before_ the next instruction?? <-
dec $01
...
(has influence on the irq code, i.e. wether an INC $01 at the beginning suffices or a LDA#$35:STA$01 is a must -> +2 bytes :/)


Even more benefit would most probably come together when misusing that CIA1-IRQ of the basic startup for init when using timer irqs instead of raster irqs. But I'll stop now, toooo much text already :)
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