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Forums > C64 Coding > TIL: The instruction after SEI can be executed before a pending IRQ is handled
2017-11-07 16:56
Krill

Registered: Apr 2002
Posts: 902
TIL: The instruction after SEI can be executed before a pending IRQ is handled

As described here: http://visual6502.org/wiki/index.php?title=6502_Timing_of_Inter..

I never knew this, after all those years, and thought i'd share this as a heads-up.

Thanks to bubis for pointing it out to me!
 
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2017-11-13 18:59
spider-j

Registered: Oct 2004
Posts: 133
Quoting Krill
If you scroll up a bit to some of MagerValps comments:

Ah okay, saw his code example also now. Didn't see that earlier. That probably happens when you're half-assed reading csdb threads while working... Thx.
2017-11-13 19:23
Groepaz

Registered: Dec 2001
Posts: 8275
"Clearing $d019 is necessary, and testing a bit more it seems like it's necessary even on a freshly reset machine."
could you provide a testcase for this? sounds like something that should be checked if it behaves the same in VICE :)
2017-11-13 22:17
Copyfault

Registered: Dec 2001
Posts: 216
Quoting Krill
Quoting Copyfault
Is it possible to have an IRQ execution directly after the write cycle of that STA $D019? [...] (has influence on the irq code, i.e. wether an INC $01 at the beginning suffices or a LDA#$35:STA$01 is a must
You ack a possibly pending raster IRQ with the write access to $d019, but any potentially arising subsequent raster IRQ condition should not trigger an actual IRQ before you enable the raster IRQs via $d01a. This will be when you have already set up your IRQ handler, and that one will behave and properly backup and restore $01. So i guess INC $01 works.

So true! Sorry for my confusion, but actually I meant $D01A, not $D019. So, now hopefully the correct question: can a raster IRQ be triggered directly after writing to $D01A? My understanding would be that even if an IRQ condition is active directly after the $D01A-write, the IRQ routine should not be processed before the next instruction has been finished. So my assumption is as follows:
...
lda #$01
sta $d01a
-> irq condition here... <-
dec $01
-> ...is processed here <-
(so INC $01 at the beginning of the IRQ code would suffice)

Is this correct?
2017-11-14 15:25
MagerValp

Registered: Dec 2001
Posts: 891
The VIC will register a pending raster IRQ whenever it reaches the raster line specified in $d011/12, regardless of the state of $d01a. So yes, when you enable $d01a, unless you cleared $d019 just before, you will trigger a raster IRQ before the next instruction.

It's easy to demonstrate using the VICE monitor:
(C:$0218) > d011 9b ff          ; Set IRQ line to 511, i.e. never
(C:$0218) > d019 ff 00          ; Disable VIC IRQs and clear pending
(C:$0218) x                     ; Run for a couple of frames
(C:$ea7e) m d019 d01a           ; Verify that no IRQ has been latched
>C:d019  70 f0
(C:$d0a9) > d011 1b             ; Set IRQ line to 255
(C:$d0a9) x                     ; Run for a couple of frames
(C:$021a) m d019 d01a           ; Verify that a raster IRQ has been latched
>C:d019  71 f0
(C:$0216) z                     ; Step one instruction, we're in keyboard polling
.C:0218  85 CC       STA $CC        - A:00 X:FF Y:2E SP:f2 ..-...ZC    2515975
(C:$0218) > d01a 01             ; Enable raster IRQ
(C:$0218) z                     ; Next instruction is IRQ handler
.C:ff48  48          PHA            - A:00 X:FF Y:2E SP:ef ..-..IZC    2515985
So, just ignore my previous speculation about $d019 (I should have tested before posting :) and use the IRQ setup routine from comment #26.
2017-11-14 15:31
Krill

Registered: Apr 2002
Posts: 902
Are we certain that VICE works correctly there? Things like various cycle delays and internal pipelining aren't perfect yet, afaik, hence groepaz asking for test programs whenever possible. :)
2017-11-14 15:54
Groepaz

Registered: Dec 2001
Posts: 8275
indeed, especially how registers behave after powerup and/or reset is always questionable, because its documented rather poorly (if at all).
2017-11-14 16:17
Oswald

Registered: Apr 2002
Posts: 4126
nice, didnt know that d019 is almost always on, nice insight.
2017-11-14 17:42
Groepaz

Registered: Dec 2001
Posts: 8275
btw, i wouldnt trust the VICE monitor to do such testing even IF the implementation in VICE is generally correct - the sideeffects (like clearing latches when reading) may or may not behave as expected. better make a small test program and verify it on a real c64.
2017-11-14 20:53
MagerValp

Registered: Dec 2001
Posts: 891
If simple stuff like this didn't work correctly in VICE there'd be tons of glitching demos, but of course it never hurts to verify: pendingirq.prg. RUN it, then, in order:

SYS49152 - no latched IRQ turns border black
SYS49194 - latched IRQ turns border white
SYS49208 - triggered IRQ turns border green

VICE matches my HMOS C64.
2017-11-15 10:04
Krill

Registered: Apr 2002
Posts: 902
Quoting MagerValp
If simple stuff like this didn't work correctly in VICE there'd be tons of glitching demos
Of course the general behaviour can easily be verified on the real thing and implemented in an emulator. But the question was something in the realm of 1-cycle delay or not, i.e., if an IRQ that is triggered pretty much at the exact cycle the IRQ mask is set would cause the CPU to execute the interrupt handler right away or only an instruction later. This requires a much more complicated setup to determine and verify.
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