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Krill
Registered: Apr 2002
Posts: 2839 |
TIL: The instruction after SEI can be executed before a pending IRQ is handled
As described here: http://visual6502.org/wiki/index.php?title=6502_Timing_of_Inter..
I never knew this, after all those years, and thought i'd share this as a heads-up.
Thanks to Bubis for pointing it out to me! |
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Oswald
Registered: Apr 2002
Posts: 5017 |
Quote: Clearing $d019 is necessary, and testing a bit more it seems like it's necessary even on a freshly reset machine. SEI/CLI is still useless though, and only creates the problem of having to clear $dc0d.
relying on things that are not under your control is usually a bad idea. (machine is in an after reset state). this is much more of a cargo cult, than using SEI/CLI. |
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Bitbreaker
Registered: Oct 2002
Posts: 500 |
After all, why bother about those few wasted bytes, where's the highly optimized demo parts? :-D How can this behaviour finally be misused? By having the upcoming instruction of the SEI on a register being read or not? |
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Krill
Registered: Apr 2002
Posts: 2839 |
Since the succeeding opcode is merely fetched, and not executed, then the pipeline flushed and the interrupt handled, then the opcode re-fetched and finally executed...
I can only imagine some arcane anti-cracking/debugging/reverse-engineering setup there, nothing demo-worthy. |
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TWW
Registered: Jul 2009
Posts: 541 |
Morale of the story is:
SEI/CLI your init. take care of unwanted IRG/NMI events from smegging up your shit. Let the byte optimizers optimize^^ |
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ChristopherJam
Registered: Aug 2004
Posts: 1378 |
Quoting TWWMorale of the story is:
SEI/CLI your init.
You appear to have forgotten the word "don't"
Just use MagerValp's routine from comment 26, and you'll be fine. SEI/CLI does nothing but create a problem that requires additional handling. |
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ChristopherJam
Registered: Aug 2004
Posts: 1378 |
Quoting KrillSince the succeeding opcode is merely fetched, and not executed, then the pipeline flushed and the interrupt handled, then the opcode re-fetched and finally executed...
I can only imagine some arcane anti-cracking/debugging/reverse-engineering setup there, nothing demo-worthy.
Yes, you'd have to be running code stored in read-sensitive IO registers, at the precise cycle an IRQ is expected. I find it hard to imagine any kind of scenario where that would save you any cycles or memory. |
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Oswald
Registered: Apr 2002
Posts: 5017 |
Quote: Quoting TWWMorale of the story is:
SEI/CLI your init.
You appear to have forgotten the word "don't"
Just use MagerValp's routine from comment 26, and you'll be fine. SEI/CLI does nothing but create a problem that requires additional handling.
good luck with that when an irq midst your interrupt setup interferes with your initialization. |
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lft
Registered: Jul 2007
Posts: 369 |
The only interrupt source that is enabled at program start is CIA1. And we disable all CIA1 interrupts. So where would the interference come from again? |
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Oswald
Registered: Apr 2002
Posts: 5017 |
Quote: The only interrupt source that is enabled at program start is CIA1. And we disable all CIA1 interrupts. So where would the interference come from again?
assumption is the root of all bugs. if you change enviroment you're facing hrs of debugging until you find the faulty non sei/cli irq setup, that relies on having the system in a known state. |
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Oswald
Registered: Apr 2002
Posts: 5017 |
anyhow I realise this is a religious argument, everyone should just do it as he likes. doesnt really matter. |
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