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Krill
Registered: Apr 2002
Posts: 2839 |
TIL: The instruction after SEI can be executed before a pending IRQ is handled
As described here: http://visual6502.org/wiki/index.php?title=6502_Timing_of_Inter..
I never knew this, after all those years, and thought i'd share this as a heads-up.
Thanks to Bubis for pointing it out to me! |
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Krill
Registered: Apr 2002
Posts: 2839 |
Are we certain that VICE works correctly there? Things like various cycle delays and internal pipelining aren't perfect yet, afaik, hence groepaz asking for test programs whenever possible. :) |
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chatGPZ
Registered: Dec 2001
Posts: 11108 |
indeed, especially how registers behave after powerup and/or reset is always questionable, because its documented rather poorly (if at all). |
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Oswald
Registered: Apr 2002
Posts: 5017 |
nice, didnt know that d019 is almost always on, nice insight. |
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chatGPZ
Registered: Dec 2001
Posts: 11108 |
btw, i wouldnt trust the VICE monitor to do such testing even IF the implementation in VICE is generally correct - the sideeffects (like clearing latches when reading) may or may not behave as expected. better make a small test program and verify it on a real c64. |
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MagerValp
Registered: Dec 2001
Posts: 1055 |
If simple stuff like this didn't work correctly in VICE there'd be tons of glitching demos, but of course it never hurts to verify: pendingirq.prg. RUN it, then, in order:
SYS49152 - no latched IRQ turns border black
SYS49194 - latched IRQ turns border white
SYS49208 - triggered IRQ turns border green
VICE matches my HMOS C64. |
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Krill
Registered: Apr 2002
Posts: 2839 |
Quoting MagerValpIf simple stuff like this didn't work correctly in VICE there'd be tons of glitching demos Of course the general behaviour can easily be verified on the real thing and implemented in an emulator. But the question was something in the realm of 1-cycle delay or not, i.e., if an IRQ that is triggered pretty much at the exact cycle the IRQ mask is set would cause the CPU to execute the interrupt handler right away or only an instruction later. This requires a much more complicated setup to determine and verify. |
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chatGPZ
Registered: Dec 2001
Posts: 11108 |
also, i was referring to the reset behaviour mostly :) |
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Oswald
Registered: Apr 2002
Posts: 5017 |
I thought it was established that the instr is only fetched ?
"Since the succeeding opcode is merely fetched, and not executed, then the pipeline flushed and the interrupt handled, then the opcode re-fetched and finally executed.." |
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Krill
Registered: Apr 2002
Posts: 2839 |
I was referring to Copyfault's last question in post #85. |
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MagerValp
Registered: Dec 2001
Posts: 1055 |
Quote: Quoting MagerValpIf simple stuff like this didn't work correctly in VICE there'd be tons of glitching demos Of course the general behaviour can easily be verified on the real thing and implemented in an emulator. But the question was something in the realm of 1-cycle delay or not, i.e., if an IRQ that is triggered pretty much at the exact cycle the IRQ mask is set would cause the CPU to execute the interrupt handler right away or only an instruction later. This requires a much more complicated setup to determine and verify.
Sure, and while it's an interesting question, we're then beyond the simple needs of an initial, unstable, raster IRQ setup. Whatever synchronization method you use for the stable IRQ will make it moot. I would still be very surprised if x64sc didn't emulate this particular detail accurately. I can't be arsed to build a test program for that detail right now anyway :)
Oh, and regarding Copyfault's question in #85, the VIC-II can trigger a raster IRQ during the sta $d01a instruction, so no, you're never guaranteed to execute the following instruction before the first IRQ. |
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