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2020-01-20 16:20

Krill

Registered: Apr 2002
Posts: 2821

Shortest code for stable raster timer setup

While working on my ICC 2019 4K entry (now postponed to ICC 2020, but i hope it'll be worth the wait), i came up with this (14 bytes):

initstabilise   lda $d012
                ldx #10          ; 2
-               dex              ;   (10 * 5) + 4
                bpl -            ; 54
                nop              ; 2
                eor $d012 - $ff,x; 5 = 63
                bne initstabilise; 7 = 70

                [...]; timer setup

The idea is to loop until the same current raster line is read at the very beginning (first cycle) and at the very end (last cycle) of a raster line, implying 0 cycles jitter.

With 63 cycles per line on PAL, the delay between the reads must be 63 cycles (and not 62), reading $d012 at cycle 0 and cycle 63 of a video frame's last line (311), which is one cycle longer due to the vertical retrace.

The downside is that effectively only one line per video frame is attempted, so the loop may take a few frames to terminate, and the worst case is somewhere just beyond 1 second.

The upside is that it always comes out at the same X raster position AND raster line (0), plus it leaves with accu = 0 and X = $ff, which can be economically re-used for further init code.

Now, is there an even shorter approach, or at least a same-size solution without the possibly-long wait drawback?

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2020-11-29 00:22

Copyfault

Registered: Dec 2001
Posts: 466

Found another one, but alas this time fully mem-adress-fixed:

$183c a0 9e  ldy #$9e
$183e a2 19  ldx #$19
$1840 18     clc
$1841 10 fa  bpl $083d

This saves another byte \o/

The CLC is just a 2-cycle place-holder that is replaced by $19 = ORA abs,Y when the SHX $19a2,Y hits the correct cycle in a badline. This ORA abs,Y effectively "eats up" the branch and ends the loop.

Mind we could also use other branch instructions (BCC springs to mind) but I decided to use BPL to avoid page-crossing (also saving a cpu cycle).

This example also shows that with SHX abs,Y and the likes, page-crossing must be carefully planned ($19a2 + y = $19a2 + $9e = $1a40, but the hi-byte is distorted s.t. it ends up as x & (hi+1) = $19 & $1a = $18).

2020-11-29 11:06

Rastah Bar

Registered: Oct 2012
Posts: 336

Quote: Found another one, but alas this time fully mem-adress-fixed:

$183c a0 9e ldy #$9e $183e a2 19 ldx #$19 $1840 18 clc $1841 10 fa bpl $083d
This saves another byte \o/

The CLC is just a 2-cycle place-holder that is replaced by $19 = ORA abs,Y when the SHX $19a2,Y hits the correct cycle in a badline. This ORA abs,Y effectively "eats up" the branch and ends the loop.

Mind we could also use other branch instructions (BCC springs to mind) but I decided to use BPL to avoid page-crossing (also saving a cpu cycle).

This example also shows that with SHX abs,Y and the likes, page-crossing must be carefully planned ($19a2 + y = $19a2 + $9e = $1a40, but the hi-byte is distorted s.t. it ends up as x & (hi+1) = $19 & $1a = $18).

The code location can't be $183c, can't it? Also the SHX instruction behaves unpredictable when a page is crossed, so I'm afraid this one won't work.

Btw, maybe you could summarize all the known allowed code locations where any SHX or SHY variant could work?

2020-11-29 14:13

Copyfault

Registered: Dec 2001
Posts: 466

Quoting Rastah Bar

The code location can't be $183c, can't it? Also the SHX instruction behaves unpredictable when a page is crossed, so I'm afraid this one won't work.

Hm, I think it should, as the SHX has $19a2 as operand bytes. Adding Y=$9e and taking the wrong fixup into account gives $19a2 + $9e = $1a40 =(wrong fixup)= $1840. This is the adress of the CLC.

So starting the code at $183c is mandatory for that sniplet to work.

Quoting Rastah Bar

Btw, maybe you could summarize all the known allowed code locations where any SHX or SHY variant could work?

I remember CJam had examined this in detail and posted it in some thread here on csdb. After a short forum scan I found it: https://csdb.dk/forums/?roomid=11&topicid=94460.

CJam summarised his findings in a very nice table (adjusted to SHX):

high byte of address written to, when:
 +--------+------------------+---------------+
 |        | no DMA on cycleN | DMA on cycleN |
 +--------+------------------+---------------+
 |page    |                  |               |
 |not     |        H         |       H       |
 |crossed |                  |               |
 +--------+------------------+---------------+
 |page    |                  |               |
 |crossed |     X&(H+1)      |   X&(H+1)     |
 |        |                  |               |
 +--------+------------------+---------------+

value written, when:
 +--------+------------------+---------------+
 |        | no DMA on cycleN | DMA on cycleN |
 +--------+------------------+---------------+
 |page    |                  |               |
 |not     |     X&(H+1)      |       X       |
 |crossed |                  |               |
 +--------+------------------+---------------+
 |page    |                  |               |
 |crossed |     X&(H+1)      |       X       |
 |        |                  |               |
 +--------+------------------+---------------+

Here H is the hi-byte of the SHX-operand. For my example, this means there's page-crossing all the time (since y=$9e)- luckily, the strange hi-byte-fixup does not depend on the DMA-at-cylce-N-condition.

2020-11-29 15:46

Rastah Bar

Registered: Oct 2012
Posts: 336

Thanks! I should have looked at the latest version of the "No More Secrets" document.

2020-12-02 01:24

Copyfault

Registered: Dec 2001
Posts: 466

Quoting Rastah Bar

Thanks! I should have looked at the latest version of the "No More Secrets" document.

True that! Should've used the opportunity to do some advertisment for this fine document - my group fellow Groepaz does an outstanding job creating and continuously extending it!

Quoting Rastah Bar

[...]The (currently) shortest code that can be placed anywhere was proposed in post #44.

Well, I feel like a little correction is appropriate:
1. while the approach with the timers is fine and I really like it, it still depends on the timers being correctly set. Ok for most init situations, but in general dangerous to rely on.
2. The "code bracket approach" introduced by CJam (post#23) and the pure LDA-variant thereof I posted in #31 are also 12 (or even 10) bytes long (still arguable if that LDY #val must really be counted, but ok) and have no mem location constraints other than the fact that some lines of code must be put inside of this "bracket".

Quoting Rastah Bar

Quiss came up with a very bright idea in post #50 that uses the instabilities of the SHX instruction. It uses less RAM, but it has some restrictions on code location. Shorter variants were found, but they have much stronger location restrictions.

So let's get rid of these location restrictions;) Since all the routines are meant to be run during init, why not let the sync loop do some init'ing also? So if we want a zp-adress zp_pos=$00..$fe to be init'ed with an initval(!=0), this routine will do it:

      ldx #initval
      ldy #<(zp_pos+1)
loop: shx $ffff,y
      lda <($100 + zp_pos - initval),x
      beq loop

The routine ends with accu=initval, which is also stored in at zp_pos in the zeropage. It works from any mem location. Only restriction is that zp_pos=$ff is not permitted. It can be shortened even further iff special init values and/or zp-adresses are used (got it down to 8 bytes so far), but I leave it as is now.

Will check codebase within the next days and add some of the routines of this thread, unless someone tells me it's already up there.

2020-12-02 13:33

Rastah Bar

Registered: Oct 2012
Posts: 336

The STA $ZP instruction (see post #44) can be made part of the init code, which reduces the timer-based stabilization approach to effectively 10 bytes:

      ldy #init_value  ;Init code
sync: lax $dc04
      sbx #51
      sty ZP      ;RRW instruction. Part of init code.
      cpx $dc04
      bne sync:

STY ABS is also allowed, in combination with SBX #52.

If I'm not mistaken, this should work on PAL, NTSC, and DREAN, but the loop exit cycle may depend on the system.

2020-12-02 18:13

Copyfault

Registered: Dec 2001
Posts: 466

Quoting Rastah Bar

The STA $ZP instruction (see post #44) can be made part of the init code, which reduces the timer-based stabilization approach to effectively 10 bytes:

ldy #init_value ;Init code sync: lax $dc04 sbx #51 sty ZP ;RRW instruction. Part of init code. cpx $dc04 bne sync:

STY ABS is also allowed, in combination with SBX #52.

If I'm not mistaken, this should work on PAL, NTSC, and DREAN, but the loop exit cycle may depend on the system.

But we both agree that this is not the shortest, but rather one of the shortest approaches that work without mem loc constraints, don't we?;) The code bracket with INCs is 10 bytes long, the other one with LDAs sums up to 10 + 2(for an LDY #val that effectively is also part of the init code) in total...

Now concerning the different VIC systems in your timer based approach, I wonder wether the operand of the sbx must be adjusted according to the no. of cycles per line or if this works with subtrahend 51 on all systems for some magic reason...

2020-12-02 18:18

Rastah Bar

Registered: Oct 2012
Posts: 336

Quoting Copyfault

ldx #initval ldy #<(zp_pos+1) loop: shx $ffff,y lda <($100 + zp_pos - initval),x beq loop

Nice! LDA <($100 + zp_pos - initval),X can simply be replaced with LDA zp_pos, I think.

2020-12-02 18:26

Copyfault

Registered: Dec 2001
Posts: 466

Quote: Quoting Copyfault

ldx #initval ldy #<(zp_pos+1) loop: shx $ffff,y lda <($100 + zp_pos - initval),x beq loop

Nice! LDA <($100 + zp_pos - initval),X can simply be replaced with LDA zp_pos, I think.

No, the loop'd take only 11 cycles which does not suffice, see also post #61 by Quiss. This was the reason to use the x-indexed version.

2020-12-02 18:26

Rastah Bar

Registered: Oct 2012
Posts: 336

Quote: Quoting Rastah Bar
The STA $ZP instruction (see post #44) can be made part of the init code, which reduces the timer-based stabilization approach to effectively 10 bytes:

ldy #init_value ;Init code sync: lax $dc04 sbx #51 sty ZP ;RRW instruction. Part of init code. cpx $dc04 bne sync:

STY ABS is also allowed, in combination with SBX #52.

If I'm not mistaken, this should work on PAL, NTSC, and DREAN, but the loop exit cycle may depend on the system.
But we both agree that this is not the shortest, but rather one of the shortest approaches that work without mem loc constraints, don't we?;) The code bracket with INCs is 10 bytes long, the other one with LDAs sums up to 10 + 2(for an LDY #val that effectively is also part of the init code) in total...

Now concerning the different VIC systems in your timer based approach, I wonder wether the operand of the sbx must be adjusted according to the no. of cycles per line or if this works with subtrahend 51 on all systems for some magic reason...

CJam's approach also takes 10 bytes, but maybe it requires blanking the screen? I'm not sure, but if it does, it is an extra constraint, since you do not always want that. For example, in a demo you can have some effect working on the startup screen, and then you don't want to blank it.

VIC always steals the same amount of cycles from the CPU on a badline. This is system independent.

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