!section "extra", sections.main.end

; stuff

!section "main", $801

; more stuff

!macro jsrf(a)
  lda #a>>16 ; load bank
  ; Do magic
  jsr a ; (top bits ignored as normal)
}

!section "bank5", $05a000
my_code:
   nop
   rts
!section "bank6", $06a000
   nop
   jsrf my_code

stuct Section
    string name
    uint32 start
    uint32 size
    uint32 current_pc
    uint32 offset
    uint8 data[]
    uint32 flags
    uint8 fillchar

!segment ROM_BANK1, $8000-$A000, READ_ONLY { ;a "segment"

[some read only stuff that can't use self-modifying code etc]

!section NAME_OF_SECTION, relativepc=$0800 { ;a "section" inside the segment

[some stuff that is intended to be copied "manually" from the ROM to $0800 in RAM. This should be able to override the READ ONLY restriction that otherwise applies to the segment that contains this section.]
}

[some more read only stuff that can't use self-modifying code etc]

}

!section "bank5", $058000

  jsr copy_fn
  jsr $c000
  rts  

copy_fn:
  stx ram_fn_end-ram
$ lda ram_fn,x
  sta $c000,x
  dey
  bne -
  rts
  
  !pc $c000
ram_fn:
  nop
  rts

!section "ram_fn", start=sections.bank5.end, pc=$c000
ram_fn:
  nop
  rts

* = Location in ROM File
IRQ_NTSC_START
.dsection sIRQ_NTSC
IRQ_PAL_START
.dsection sIRQ_PAL

.logical IRQ_DEST ; make the code assemble as if its in RAM
.section IRQ_NTSC
.section IRQ_NTSC_ENTER
.block IRQ_NTSC
IRQ_ENTER 
...code..
.ends 
.align size(IRQ_NTSC_ENTER) >? size(IRQ_PAL_ENTER) ; make sure first is in the same sport
IRQ_FIRST
...code...

IRQ_SECOND
...code...

IRQ_THRID
...code...

.bend ; NTSC IRQ
.ends; NTSC IRQ Handler
.here

.logical IRQ_DEST
.section sIRQ_PAL
.section IRQ_PAL_ENTER
.block IRQ_PAL
IRQ_ENTER 
...code..
.ends 
.align size(IRQ_NTSC_ENTER) >? size(IRQ_PAL_ENTER) ; make sure first is in the same sport
IRQ_FIRST
...code...

IRQ_SECOND
...code...

IRQ_THRID
...code...

.bend
.ends; PAL IRQ Handler
.here 

IRQ_DEST
.fill size(sIRQ_NTSC) ?> size(sIRQ_PAL)
IRQ_FIRST = IRQ_PAL.IRQ_FIRST
cerror IRQ_NTSC.IRQ_FIRST != IRQ_PAL.IRQ_FIRST, "align filed" 

                        #segdef "bank0",$8000-$A000, fillup, force, $bb, abs
                        #segdef "bank1",$8000-$A000, fillup, force, $bb, abs

                        #outfile @, "bank0", "bank1"

                        #include "macros.src"

                        #include "bank0.src"
                        #include "bank1.src"

#if segmentof {subroutine} != BANKNAME 

copy:
   nop
.loop
   dex
   beq .loop

al C:1004 .PL_SP1_chn01
al C:1022 .PL_SP2_chn01
al C:103f .PL_SETPARAMFLAG_chn01
al C:1043 .PL_PARAM_chn01
al C:1048 .PL_SETNOTEFLAG_chn01
al C:104c .PL_NOTE_chn01
al C:1057 .PL_SP1_chn02
al C:1075 .PL_SP2_chn02
al C:1092 .PL_SETPARAMFLAG_chn02
al C:1096 .PL_PARAM_chn02
al C:109b .PL_SETNOTEFLAG_chn02
al C:109f .PL_NOTE_chn02
al C:10aa .PL_SP1_chn03
al C:10c8 .PL_SP2_chn03
al C:10e5 .PL_SETPARAMFLAG_chn03
al C:10e9 .PL_PARAM_chn03
al C:10ee .PL_SETNOTEFLAG_chn03

.local_symbol = 3
    .print .local_symbol
    lda #.local_symbol
    beq .skip
.skip
    rts

!section "ZP", start=$00, size=$100, flags=NoStore
!section "RAM", start=$801, size=$9f00-$0801, flags=NoStore
;!section "HIRAM", start=$a000, size=$2000, NoStore
!memory "HIRAM",$a000,$2000

!section "DATA", in="RAM", flags=NoStore


!section "main", in="RAM", flags=First {
    !section "ZP" {
        var0: !ds 1
    }
start:
    sei
    !section "sine" in="DATA" {
        sine: !rept 256 { !byte sin(i) }
    }
    lda sine,x
    sta var0
}

; Put pointer to given string or array in XY
!macro xyptr(a) {
    !section "DATA" {
.local
        !fill a
    }
    ldx #>.local
    ldy #<.local
}

!section "extra", in="HIRAM" {

}

!section "other", in="HIRAM" {

}

!section <args...> [ { <statements> } ]

; Root sections
!section "RAM" start=$0000 size=64*1024 NoStore
!section "ZP" start=$00 size=256 NoStore

; Non-leaf section
!section "text" in="RAM" NoStore Last

; Leaf section
!section "code" in="RAM", start=$801 {
    ; Basic start and such
    ; Another leaf section, defined recursively
    !section in="text" {
        name: !text "name"
    }
    lda name,x
}

; constant D011VALUE == value in d011

D011VALUE = 0

!macro DrawRasterColors(row) {
    !if (row & 7) == (D011VALUE & 7) {
    ; 23 cycle macro
    col[row]:
        lda #0                  ;  2
        sta $d020               ;  6
        sta $d021               ; 10
        !rept 5 { nop }
        bit $ea                 ; 23
    } else {
    ;63 cycle macro
    col[row]:
        lda #0                  ;  2
        sta $d020               ;  6
        sta $d021               ; 10
        !rept 25 { nop }
        bit $ea                 ; 63
    }
}

!section "main", $c000

!rept 6*8 {
    DrawRasterColors(i + $40)
}

!test "bad" {
    DrawRasterColors(0)
}
!assert tests.bad.cycles == 23

!test "good" {
    DrawRasterColors(1)
}
!assert tests.good.cycles == 63

!test "modify" {
    lda #9
    sta col[$40]+1
    lda #8
    sta col[$41]+1
}
!assert tests.modify.ram[$c001] == 9
!assert tests.modify.ram[$c010] == 8

    !script "../lua/sid.lua"

    data = load("../data/test.sid")
    sid = sid_parse(data)
    
    !section "music", sid.load
music:
    !fill sid.data

%{

    sid_data = nil

    function generate_data()

        map_bank_write(0xd4, 1, function(adr, val)
            if sid_data then
                table.insert(sid_data, adr - 0xd400)
                table.insert(sid_data, val)
            end
        end)

        start_run()
        init = sym("sid.init")
        play = sym("sid.play")
        set_a(0)
        call(init)
        sid_data[#sid_data - 1] = sid_data[#sid_data - 1] | 0x80
        for i=1,15*50 do
            l = #sid_data
            call(play)
            if l ~= #sid_data then
                sid_data[#sid_data - 1] = sid_data[#sid_data - 1] | 0x80
            else
                print("Silent frame")
            end
        end
    end

    function get_sid_data()
        sid_data = {}
        generate_data()
        result = sid_data
        sid_data = nil
        return result
    end
}%

    !text "SID"
sid_data:
    !fill get_sid_data()

Top Coders
	
1 Raistlin  (9.8)
2 Graham  (9.8)
3 Crossbow  (9.8)

!delay <cycles>, <regs_to_preserve>

!merge <section1>, <secition2>, <max_cycles>