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Forums > C64 Coding > VIA 6522 latching still unemulated.
2021-04-08 13:12
Zibri

Registered: May 2020
Posts: 159
VIA 6522 latching still unemulated.

let's imagine that on disk are recorded 5 bytes:
we call them x1 x2 x3 x4 and x5

now imagine we positioned in front of them, we skip 3 and read the fourth.
if to do that you use this code:

    CLV
    LDA $1C01   ; A here contains X1
    LDY #$03
loop:
    BVC loop
    CLV
    DEY
    BNE loop
    LDA $1C01 ;  A = X1 on RH and X5 on emulators


on vice, pi1541 and ultimate64/u2+
A will contain "x5".
But on real hardware it will contain X1.

The following code instead will work on both:
        CLV
        LDA $1C01   ; A here contains X1
        LDY #$03
loop:
        BVC loop
        CLV
        DEY
        BNE loop
        LDA $1C0F ; A = X5


That happens because 1C01 keeps the last byte READ (with any LOAD operation or any other cpu instruction that does a READ) while 1C0F contains the actual shift register.

Note:
also putting a "useless" LDA $1C01 inside the loop and the reading 1C01 will work too. But still I think that's an important feature present on BOTH VIA CHIPS that should be emulated.
 
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2021-04-12 13:13
Zibri

Registered: May 2020
Posts: 159
Quoting Martin Piper
Well some floppy manufacturers that did protection products did degauss their floppies first and then use highly calibrated and time controlled disk writers (using a sync hole) that could create areas that effectively lacked magnetic information. They would be read as noise and have data read timing characteristics that were very hard to reproduce in drives without the sync hole and calibration.

Also this while it's theoretically possible (and reproducible) from a 1541 point of view doesn't change much. What counts is what the 1541 is physically able to read "reliably". Anything "unreliable" would be intepreted in different ways by different drives in different conditions.
2021-04-12 13:15
Zibri

Registered: May 2020
Posts: 159
Quoting ChristopherJam
Quoting Groepaz
That kind of stuff even varies between real drives, eg the "long board" will allow reading more zeros in a row reliably.

I gather from the comments in the pi1541 sources that at least one of the drives physically cannot read more than three zeros in a row, as there's a timer circuit that just spits out a continuous loop of 100010001000, unless it sees a flux change in which case it restarts the loop from a point half a bit before the next 1 is emitted.

Is there a difference between long and short boards in that regard?

Funny you mentioned it. pi1541 abd Vice are the ones who behave very differently in the presence of zeroes.
Also OC118 drive writes and reads less zeroes in a row than a 1541.
The best I have seen so far on emulators is the u2+/u64.
2021-04-12 13:19
Zibri

Registered: May 2020
Posts: 159
Quoting Groepaz
Quote:
Well some floppy manufacturers that did protection products did degauss their floppies first and then use highly calibrated and time controlled disk writers (using a sync hole) that could create areas that effectively lacked magnetic information. They would be read as noise and have data read timing characteristics that were very hard to reproduce in drives without the sync hole and calibration.

using non preformatted disks and then duplicating with the so called "trace machine" was pretty much the standard process for floppy duplicating :) unformatted areas are not what is typically referred to as "weak bits" though. (and protections based on this are actually easy to fool by writing something like a 10000100000 pattern, ie more or less random chunks 4 or more zeroes with ones in between)
Quote:
I don't think this behaviour is different between long and short (custom IC)

Somehow that is what i remember though. It might not be directly related to the data seperator, but some other detail.

Exactly: specific patters with different sequences of "0" bits produce predictable results.
By analyzing those results on RH an emulators, pi1541 and Vice can be easily identified.
u2 and u64 instead behave like a (too) perfect 1541.
2021-04-12 13:21
Groepaz

Registered: Dec 2001
Posts: 9973
Quote:
I was meaning that the ones "written with reduced write current" didn't really exist or they are just the byproduct of bad media or bad drives. They were never used as a protection system

Thats quite a claim - how do you know this? (US Patent 4849836 shows a few more rarely used methods to create weak bits)
Quote:
Exactly: specific patters with different sequences of "0" bits produce predictable results.

no. what you will read is more or less random noise, not predictable (on real drives, obviously).
2021-04-12 16:04
ChristopherJam

Registered: Aug 2004
Posts: 1174
Quoting tlr
This is part of the clock recovery "PLL". If the bitrate from disk is slightly slower than the reference bitrate you will occasionally get a one bit as your third bit. This is due to the sequence wrapping before the whole last '0' was passed. This mean unless the bitrates are crafted in a special way, only two consecutive '0's may be used reliably (but see below).

Oh that part I'm well aware of - but you need the reading drive to run at 8/7ths of the speed of the writing drive for 10001 to read as 1001, or 8/9ths to read 10001 as 100011. Even the latter would require a 36rpm difference between the speeds of the two drives, which seems a tad unlikely, no?

(As I understand it, the first "1" is declared two quarterbits after the flux is detected, then "0"s declared at six, ten, and fourteen quarterbits).

Quote:
I don't think this behaviour is different between long and short (custom IC), but IIRC there are other issues relating to longer runs on later drive models, i.e noise gradually taking over generating spurious bits and possibly a recovery time after long '0' runs. Someone else could perhaps fill in here? I never had a later drive myself.

Yes, I suspect the automatic gain control is more likely to be an issue in practice - the longer the gap between flux changes the more likely it is that the drive will amplify noise to the point that it reads as a spurious 1 bit.
2021-07-18 03:22
willymanilly

Registered: Jan 2016
Posts: 27
Just stumbled accross this thread!

Quoting Groepaz
Those VIA Datasheet arent actually very useful to understand the detail behaviour of the VIAs (and they contain various mistakes too).


Couldn't agree more with this statement! :) Is it possible the following extract is one of the mistakes you mention? See below for context. :)
"The PA port and the PB port on the R6522 can be enabled in the Auxiliary Control Register (Figure 14) to be latched by their individual port control lines (CA1, CB1). Latching is selectable to be on the rising or falling edge of the signal at each individual port control line"

Quoting Krill
As Groepaz implies, there is a reason why two of the most popular emulators don't do this right. (Does Z64K, btw.? :D)


Z64K has latching implemented but Freespin exposed a bug with it which caused the demo to get stuck on track 1. Other emulators with a VIA port latch "fix" also get stuck at track 1.

Looking at part of the Freespin loader source, if the 6522 datasheet is to be believed, storing 6f into 1c0c should cause the latching to occur on a positive edge instead of the usual negative edge.

// switch from square wave generation to loading
lda #$6f
sta $1c02
sta $1c0c // ee is the default, but 6f works, too.
lda #$41
sta $1c0b

The "hack" I ended up implementing in Z64K to support Freespin and to not break the latching behaviour mentioned in VICE bug #582 was to force the latch to always occur on a negative edge when latching is enabled. The IRQ still uses the value in the ACR to determine what edge to trigger on. There's still parts of the latch emulation that does not strictly follow the information contained in the datasheet so it won't surprise me if something new comes out and breaks the latching emulation again.

Quoting Zibri
I agree with you at a logical level but still since emulators EMULATE real hardware, they should emulate as much as they can and this is very easy to fix.

We do our best but implementing features based purely on high level documentation is actually very challenging because it does not always give the full picture of what's happening at the low level. This is where a test suite of programs where the results have been confirmed on real hardware like the ones available in Testbench are very useful and can make things so much easier to fix.
2021-07-18 14:27
Groepaz

Registered: Dec 2001
Posts: 9973
I am still waiting for the apparently very easy to do patch that fixes it :)
2021-07-19 18:32
Quiss

Registered: Nov 2016
Posts: 22
It seems that $6f in $1c0c causes loading to break on (some) real hardware, as well. In particular, I just received word that an 1541 with an older Alps drive mechanism (and a short board) won't run Freespin either, but works fine if $1c0c is set $ee.
2021-07-19 18:42
Groepaz

Registered: Dec 2001
Posts: 9973
would be awesome if you could knock up a couple small test programs for this stuff :)
2021-07-19 22:25
willymanilly

Registered: Jan 2016
Posts: 27
Quote: It seems that $6f in $1c0c causes loading to break on (some) real hardware, as well. In particular, I just received word that an 1541 with an older Alps drive mechanism (and a short board) won't run Freespin either, but works fine if $1c0c is set $ee.

I'm light of Freespin failing on some real hardware I'm thinking now the issue is more likely to do with the length of the byte ready signal which triggers the port latching.

$ee in 1c0c should always guarantee valid data will be on the port pins because it triggers as soon as the byte ready signal asserts itself. If $6f is used the latching may occur when the shifter has already shifted another bit depending on when the byte ready signal resets itself.

Another useful test would be to determine how long the byte ready signal is for different drive models. I've already tested in emulation that shortening the length of the byte ready signal allows Freespin to run the complete demo without requiring a hack to the VIA port latching!
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