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Krill
Registered: Apr 2002
Posts: 2839 |
Alt-history no-cost design changes with great value
Which things in the C-64 could have been implemented or connected differently without conceivable extra cost, for coding advantages?
Thinking of things like shuffling the chip register bits like VIC's $d011 and $d016 differently (such that some effects can be achieved with fewer register writes or less twiddling).
Or putting some IO register to $01 (and move the memory configuration somewhere else, somehow).
Maybe also having different PLA memory configurations (not necessarily more).
Or connecting external signals to the CIA port pins in a different order.
Discuss! =) |
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XmikeX
Account closed
Registered: Oct 2018
Posts: 2 |
FUCKINGS TO C64 ..! .. err, my apologies.
... What I mean is .. How about something like .. replace 6510 with 6502C from Atari and get a true Halt .. instead of that BA stuff ! (??)
--
.. now .. Let's continue with the beloved C-128, and the missing "improvements" there ! .. of course !
C-128 was slated to have ...
- FULL 4 MHZ operation, across the board, no more Z80 waits!
- A real 6551 chip (at $d700, as seen in CP/M3 source) !
- MMU that could handle Full 256k of RAM, as noted in rom copy routine to missing ram banks !
- VDC with IRQ pin AND full 64k RAM ! (we only saw this in the 128 DCR, but as Strobe reminded me... they did not connect the /IRQ pin ! .. and yes, i know the 64k part is easy to add in the flat 128s )
MOS was incable of 4 MHz anything, so I won't bemoan lack of 4 MHz support chips, etc !
(this thread is carryover from IRCNET #c-64 discussion) |
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Mixer
Registered: Apr 2008
Posts: 422 |
C-64
- SID noise reduction.
- DMA for memory transfers/register updates. |
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Mac Bacon
Registered: Feb 2016
Posts: 6 |
Sprite pos registers would be easier to index if they were in x0,x1,x2,x3,x4,x5,x6,x7,y0,y1,y2,y3,y4,y5,y6,y7 order. |
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Krill
Registered: Apr 2002
Posts: 2839 |
Quoting MixerC-64
- SID noise reduction.
- DMA for memory transfers/register updates. Pretty sure a DMA controller would have added a few dollars to the BOM. =)
What is required for SID noise reduction?
Quoting Mac BaconSprite pos registers would be easier to index if they were in x0,x1,x2,x3,x4,x5,x6,x7,y0,y1,y2,y3,y4,y5,y6,y7 order. Can you elaborate with some examples? |
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Zaz
Registered: Mar 2004
Posts: 33 |
Nah, the C64 is perfect! |
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Martin Piper
Registered: Nov 2007
Posts: 634 |
Colour RAM address like screen RAM |
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MagerValp
Registered: Dec 2001
Posts: 1055 |
Ditching 1540 compatibility, which failed anyway. |
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Oswald
Registered: Apr 2002
Posts: 5017 |
this comes from Graham (he told me on irc aeons ago): why have the top 2 bits of char pointers ANDed to 00 in ECM mode ? just leave them as is.
also probably wouldnt cost much to have a PLA setting where VICII is not forced to see char rom at $1000 and $9000.
I'm totally with Xmikex on the Halt thing. When I learned how Atari does it I was like WTF is it so complicated on c64 then. VICII could just easily halt cpu on every 2nd 2mhz cycle, and just stop doing that on the borders for 2mhz.
proper CIA's with shift registers working into serial bus ?
also dropping potmeters from SID and lightpen from VICII for something more useful?
how about border disable bit in VICII ? probably wouldnt need more then a handful of transistors :) ... or letting badlines go into top/bottom border area..
edit: multicolor mode #2, where its always multicolor, so 16 colors possible for d800.
edit#2: also how about that unused lowmost bit in d018? wouldnt it be nice sometimes to just inc d018 ? :) |
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TWW
Registered: Jul 2009
Posts: 541 |
Another colour ram bank allowing double buffering |
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tlr
Registered: Sep 2003
Posts: 1714 |
A simpler way to sync the CPU to the VIC-II. Either via some kind of halt facility, or at least having a up-counting timer to measure how far from the time of IRQ assertion we are. |
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