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Forums > C64 Coding > Alt-history no-cost design changes with great value
2021-05-01 22:49
Krill

Registered: Apr 2002
Posts: 2804
Alt-history no-cost design changes with great value

Which things in the C-64 could have been implemented or connected differently without conceivable extra cost, for coding advantages?

Thinking of things like shuffling the chip register bits like VIC's $d011 and $d016 differently (such that some effects can be achieved with fewer register writes or less twiddling).
Or putting some IO register to $01 (and move the memory configuration somewhere else, somehow).
Maybe also having different PLA memory configurations (not necessarily more).
Or connecting external signals to the CIA port pins in a different order.

Discuss! =)
 
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2021-05-02 09:31
Oswald

Registered: Apr 2002
Posts: 5007
this comes from Graham (he told me on irc aeons ago): why have the top 2 bits of char pointers ANDed to 00 in ECM mode ? just leave them as is.

also probably wouldnt cost much to have a PLA setting where VICII is not forced to see char rom at $1000 and $9000.

I'm totally with Xmikex on the Halt thing. When I learned how Atari does it I was like WTF is it so complicated on c64 then. VICII could just easily halt cpu on every 2nd 2mhz cycle, and just stop doing that on the borders for 2mhz.

proper CIA's with shift registers working into serial bus ?

also dropping potmeters from SID and lightpen from VICII for something more useful?


how about border disable bit in VICII ? probably wouldnt need more then a handful of transistors :) ... or letting badlines go into top/bottom border area..

edit: multicolor mode #2, where its always multicolor, so 16 colors possible for d800.

edit#2: also how about that unused lowmost bit in d018? wouldnt it be nice sometimes to just inc d018 ? :)
2021-05-02 10:16
TWW

Registered: Jul 2009
Posts: 541
Another colour ram bank allowing double buffering
2021-05-02 11:03
tlr

Registered: Sep 2003
Posts: 1701
A simpler way to sync the CPU to the VIC-II. Either via some kind of halt facility, or at least having a up-counting timer to measure how far from the time of IRQ assertion we are.
2021-05-02 11:30
chatGPZ

Registered: Dec 2001
Posts: 11088
Quote:
proper CIA's with shift registers working into serial bus ?

the CIA shift registers work just fine
2021-05-02 11:52
Krill

Registered: Apr 2002
Posts: 2804
Quoting TWW
Another colour ram bank allowing double buffering
Quoting Martin Piper
Colour RAM address like screen RAM
Again, pretty sure these things like colour extra RAM or extending the entire data bus to 12 bits would have added quite a bit to price of the machine.
Please stay with no-cost changes (or very little cost if you will).

Quoting MagerValp
Ditching 1540 compatibility, which failed anyway.
So the ROM loader would be slightly faster, but still very slow? =)

Quoting Oswald
this comes from Graham (he told me on irc aeons ago): why have the top 2 bits of char pointers ANDed to 00 in ECM mode ? just leave them as is.
Very good!
Quoting Oswald
also how about that unused lowmost bit in d018? wouldnt it be nice sometimes to just inc d018 ? :)
As that bit is always 1, inc works pretty well, no? :)

Quoting Oswald
multicolor mode #2, where its always multicolor, so 16 colors possible for d800.
You mean changing multicolour char mode, which renders hires chars for colours 0-7, so it would always put out multicolour chars?
2021-05-02 14:36
TWW

Registered: Jul 2009
Posts: 541
Quoting Krill
Quoting TWW
Another colour ram bank allowing double buffering
Quoting Martin Piper
Colour RAM address like screen RAM
Again, pretty sure these things like colour extra RAM or extending the entire data bus to 12 bits would have added quite a bit to price of the machine.
Please stay with no-cost changes (or very little cost if you will).



Use bank switching and change between 2 ColRAM banks located @ $d800. 2k ram instead of 1k and PLA to handle the switching.
2021-05-02 14:55
ChristopherJam

Registered: Aug 2004
Posts: 1359
Quote: Another colour ram bank allowing double buffering

I gather c128 has that :)
2021-05-02 15:24
Jammer

Registered: Nov 2002
Posts: 1288
- TXY/TYX
- 8bit Colour RAM which uses higher nybble either for hires/mc in charmode, or luma level per char in bitmap mode (but that would probably cost a lot back then)
- parallel drive interface (we know it was compatibility decision, not cost decision)
- SID made according to original specs + filter per channel ;)
- hardware PCM channel
2021-05-02 15:26
ChristopherJam

Registered: Aug 2004
Posts: 1359
Agreed on deinterleaving the sprite position registers

Re-arranging the pulse width bits on SID to put the eight high bits in a single register would have saved a fair bit of code - most tunes could happily leave the low four bits untouched during playback.

Putting the lowest bit of sprite X position into a separate register instead of the highest would likely have resulted in a lot of routines that left the LSB zero, but would make full screen sprite positioning a hell of a lot saner if you could live with the slightly coarser movement.

Alternately, instead of seperate registers for sprite x-msb, spriority, sprite x/y expand, sprite MCM, have a mode register for each sprite that combines those five attributes (and probably the collision flags too).

Soooo much saner for multiplexers that actually change modes.

Allow disabling of the character set images in one of the memory maps (surely just a change in PLA programming).

Bugfix stx $xxxx,y and sty $xxxx,x
2021-05-02 15:34
Krill

Registered: Apr 2002
Posts: 2804
As for re-grouping registers, i always thought the SID's 7 per-voice registers should have been interleaved.
Then updating registers in a per-voice loop could be done with, e.g., X = 2, 1, 0 rather than subtracting 7.
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