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Krill
Registered: Apr 2002
Posts: 2821 |
Alt-history no-cost design changes with great value
Which things in the C-64 could have been implemented or connected differently without conceivable extra cost, for coding advantages?
Thinking of things like shuffling the chip register bits like VIC's $d011 and $d016 differently (such that some effects can be achieved with fewer register writes or less twiddling).
Or putting some IO register to $01 (and move the memory configuration somewhere else, somehow).
Maybe also having different PLA memory configurations (not necessarily more).
Or connecting external signals to the CIA port pins in a different order.
Discuss! =) |
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chatGPZ
Registered: Dec 2001
Posts: 11089 |
How would that be nice and not just be a major WTF? |
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JackAsser
Registered: Jun 2002
Posts: 1987 |
Route CHAREN, HIRAM and LORAM signals to the expansion bus. If you don't want a wider connector (more expensive carts) then just replace one of the +5V and 2 of the 4 GNDs. |
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Krill
Registered: Apr 2002
Posts: 2821 |
I guess any changes in the CPU behaviour would have been anything than cheap, though. Picking another existing CPU, ok, if produced in-house at MOS. :)
Quoting GroepazQuote:parallel drive interface (we know it was compatibility decision, not cost decision)
it was pure cost decision, the cable and connectors for ieee488 cost a small fortune back then. Yes, and with that fast serial failure...
Would have been nice to have a different layout in drive-side $1800 to write to the serial bus.
E.g., with DATA and CLK out on say bits 4 and 0, could bitbang out a byte in just 4+3*6 cycles (not 4+3*8) via STA $1800 : lsr : STA $1800 etc.
And if not that, having ATNA and CLK out on bits 1 and 0 would have been the next best thing. =) |
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ChristopherJam
Registered: Aug 2004
Posts: 1370 |
Quoting GroepazHow would that be nice and not just be a major WTF?
You could clear RAM at a hair over 2.5 cycles per byte! Epic! |
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Shadow
Account closed
Registered: Apr 2002
Posts: 355 |
Quote: A simpler way to sync the CPU to the VIC-II. Either via some kind of halt facility, or at least having a up-counting timer to measure how far from the time of IRQ assertion we are.
Yeah, this one for sure! So convenient when coding on the Atari 8-bit machines or the VCS/2600 for that matter to just do a STA WSYNC - and you are in perfect sync again.
Cycle/raster-exact code on the C64 is such a nightmare in comparison. First you have to use some convoluted methods with double IRQs or whatnot to actually get in sync, and then it's a struggle to actually keep it once you start having badlines and sprites etc.
That's why my answer when someone makes suggestion on anything I code "But couldn't thing X be in the sideborder?" the answer is always a resolute "NO!" :) |
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Krill
Registered: Apr 2002
Posts: 2821 |
Quoting ShadowThat's why my answer when someone makes suggestion on anything I code "But couldn't thing X be in the sideborder?" the answer is always a resolute "NO!" :) Too lame or lazy, in other words. :)
I think setting up a CIA timer counting 63 cycles once, then querying that after VIC raster interrupts and having a little delay slide isn't really that much hassle. Especially since you can easily re-use that piece of code. |
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Dwangi
Registered: Dec 2001
Posts: 129 |
Maybe not an answer to the original question.
But I miss the Z-register. |
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Copyfault
Registered: Dec 2001
Posts: 466 |
Another what-if idea: grouping CSEL (not RSEL, mind!) and the YSCROLL-bits together in one VIC-II-control register would sometimes help to do badline- and sideborder-stuff in one go. |
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Krill
Registered: Apr 2002
Posts: 2821 |
Quoting CopyfaultAnother what-if idea: grouping CSEL (not RSEL, mind!) and the YSCROLL-bits together in one VIC-II-control register would sometimes help to do badline- and sideborder-stuff in one go. Just have a global border-disable bit as Oswald suggested, and be done with it. :) |
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Copyfault
Registered: Dec 2001
Posts: 466 |
Quoting KrillQuoting CopyfaultAnother what-if idea: grouping CSEL (not RSEL, mind!) and the YSCROLL-bits together in one VIC-II-control register would sometimes help to do badline- and sideborder-stuff in one go. Just have a global border-disable bit as Oswald suggested, and be done with it. :) Global border-disable flag is maybe the most steroidal what-if-scenario :)
But grouping CSEL and YSCROLL is not the same and may offer other things, like: opening the sideborder and repeating the textline (and supressing badlines in the following) \o/ |
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