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Forums > C64 Coding > Alt-history no-cost design changes with great value
2021-05-01 22:49
Krill

Registered: Apr 2002
Posts: 2804
Alt-history no-cost design changes with great value

Which things in the C-64 could have been implemented or connected differently without conceivable extra cost, for coding advantages?

Thinking of things like shuffling the chip register bits like VIC's $d011 and $d016 differently (such that some effects can be achieved with fewer register writes or less twiddling).
Or putting some IO register to $01 (and move the memory configuration somewhere else, somehow).
Maybe also having different PLA memory configurations (not necessarily more).
Or connecting external signals to the CIA port pins in a different order.

Discuss! =)
 
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2021-05-03 15:53
Copyfault

Registered: Dec 2001
Posts: 466
Another what-if idea: grouping CSEL (not RSEL, mind!) and the YSCROLL-bits together in one VIC-II-control register would sometimes help to do badline- and sideborder-stuff in one go.
2021-05-03 16:19
Krill

Registered: Apr 2002
Posts: 2804
Quoting Copyfault
Another what-if idea: grouping CSEL (not RSEL, mind!) and the YSCROLL-bits together in one VIC-II-control register would sometimes help to do badline- and sideborder-stuff in one go.
Just have a global border-disable bit as Oswald suggested, and be done with it. :)
2021-05-03 17:19
Copyfault

Registered: Dec 2001
Posts: 466
Quoting Krill
Quoting Copyfault
Another what-if idea: grouping CSEL (not RSEL, mind!) and the YSCROLL-bits together in one VIC-II-control register would sometimes help to do badline- and sideborder-stuff in one go.
Just have a global border-disable bit as Oswald suggested, and be done with it. :)
Global border-disable flag is maybe the most steroidal what-if-scenario :)

But grouping CSEL and YSCROLL is not the same and may offer other things, like: opening the sideborder and repeating the textline (and supressing badlines in the following) \o/
2021-05-03 17:23
Krill

Registered: Apr 2002
Posts: 2804
Badline-disable bit, then! =)
2021-05-03 17:58
chatGPZ

Registered: Dec 2001
Posts: 11088
Hungarians suggesting global border disable. Mind: blown
2021-05-03 20:54
Count Zero

Registered: Jan 2003
Posts: 1809
Krill is already on a maker track and just collecting further suggestions? Much here sounds like you guys want some Amiga500 at 1MHz ... or a DTV or so? :)
2021-05-04 12:40
Codetsu

Registered: Feb 2017
Posts: 3
jep DTV have all that and more
no dreams it's here ready to code
2021-05-04 13:12
Krill

Registered: Apr 2002
Posts: 2804
Quoting Count Zero
Krill is already on a maker track and just collecting further suggestions? Much here sounds like you guys want some Amiga500 at 1MHz ... or a DTV or so? :)
No, this is just idle musing.

Retro ≠ Vintage,
DTV ≠ C-64.
2021-05-04 19:20
Slammer

Registered: Feb 2004
Posts: 416
Quote: Agreed on deinterleaving the sprite position registers

Re-arranging the pulse width bits on SID to put the eight high bits in a single register would have saved a fair bit of code - most tunes could happily leave the low four bits untouched during playback.

Putting the lowest bit of sprite X position into a separate register instead of the highest would likely have resulted in a lot of routines that left the LSB zero, but would make full screen sprite positioning a hell of a lot saner if you could live with the slightly coarser movement.

Alternately, instead of seperate registers for sprite x-msb, spriority, sprite x/y expand, sprite MCM, have a mode register for each sprite that combines those five attributes (and probably the collision flags too).

Soooo much saner for multiplexers that actually change modes.

Allow disabling of the character set images in one of the memory maps (surely just a change in PLA programming).

Bugfix stx $xxxx,y and sty $xxxx,x


I understand the logic behind the 'one control register for each sprite' but I would miss easy sprite stretching.
2021-06-07 23:11
dyme

Registered: Nov 2018
Posts: 14
Gravedigging, but one easy change rarely gets mentioned:

It would have been fairly easy to enable changing the hi-byte of the memory bus for accesses to the zeropage (and stack) by writing it into a fixed memory address akin to $01, or maybe some cia register.

Being able to treat every single 256byte block as zeropage would bring such a performance boost, not only because of the 3 instead of 4 cycles per lda/sta, but being able to stx addr,y and sty addr,x saves a lot of swapping registers through memory. Also SO MUCH more zeropage-pointers for zeropage indirect addressing.

Also chaining / interleaving functions by stack combined with switching the stack page midchain could... ah... I don't know, something awesome, I guess.
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