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Starfox
Registered: Jul 2014
Posts: 31 |
Sideborder open on badline
I'm just trying to see if I can remember some vic effects, like the FLD question I asked about the other day. I made those effects myself back in the day, but couldn't remember the timings etc. (even looking over my old convoluted code didn't help, lol) but got it working (thanks).
I'm now trying to open the sideborder on the first text line (line 51), which should be a badline.
I break after the stabilizing code:
txs
ldx #8
dex
bne *-1
bit $00
lda $d012
cmp $d012
beq *+2
ldx #0 // break here
ldy #$c0
lda #$c8
sty $d016
sta $d016
sty $d016
sta $d016,x
Vice tells me it is at cycle 3. After executing "ldx #0" I'm at cycle 5. Executing "ldy #$c0" and I'm at cycle 7. Executing "lda #$c8" and I'm at cycle 9, as expected.
I'm then executing "sty $d016" but I'm at cycle 51. so the instruction ends on cycle 55. One cycle short, to open the border.
Btw I have no sprites on at the moment, but I want to have one sprite in the left border, and one in the right border, and I want to have text on those lines too, so no fld.
Before I try to fix this, I just want to know if I'm on the right track or completely wrong? 😄 |
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Martin Piper
Registered: Nov 2007
Posts: 631 |
I seem to remember the side borders cannot be opened on a bad line with sprite and text/bitmap screen enabled and without FLD. The cycles aren't available at the time you need them. Unless you're using that enabled screen but disabled badline mode. |
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chatGPZ
Registered: Dec 2001
Posts: 11100 |
it can be done :) You might have to play with different instructions so the store happens in the right cycle |
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Martin Piper
Registered: Nov 2007
Posts: 631 |
Postpone the $d016 write with a RMW instruction? |
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Martin Piper
Registered: Nov 2007
Posts: 631 |
oh yes, doh, this is probably a clean example: Sideborder 4K
$265c stx $d016 - cycle 52
$265f sta $d016 - cycle 56
Note sprites 4-7 are enabled, 0-3 are disabled.
Interesting use of HSP/DMA delay as well. |
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chatGPZ
Registered: Dec 2001
Posts: 11100 |
Quote:sprites 4-7 are enabled, 0-3 are disabled
yes, this is the key :) |
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Martin Piper
Registered: Nov 2007
Posts: 631 |
Quote: Quote:sprites 4-7 are enabled, 0-3 are disabled
yes, this is the key :)
Yeah, sprite 0 fetch starts at cycle 58 with a read pre-stall 3 cycles before. |
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Krill
Registered: Apr 2002
Posts: 2825 |
The interesting point here is that the write to $d016 most likely happens just before badline DMA, and not after in cycle 56.
Any new CPU op after the badline would be to late.
So the write goes to VIC just before badline DMA, but it's only effective in that magic cycle.
Or is there a better explanation for why open sideborder on a badline is possible at all? :)
Or maybe Christian Bauer's VIC Artikel is wrong again, and badline DMA is not offset by 1 cycle/char before display, but by 5 or so, thus CPU can work again already 5 cycles before the sideborder while the badline is still being drawn? |
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Oswald
Registered: Apr 2002
Posts: 5017 |
Gunnar, I cant imagine VIC would only register d016 change 40 cycle later on a badline, just because, why ? I think instruction is stopped before its write cycle, then write cycle AND VIC checking if border needs to be started might happen at the same cpu cycle (remember vic being 8mhz) |
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chatGPZ
Registered: Dec 2001
Posts: 11100 |
Quote:remember vic being 8mhz
only the graphics sequencer |
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Krill
Registered: Apr 2002
Posts: 2825 |
Quoting OswaldI think instruction is stopped before its write cycle, then write cycle AND VIC checking if border needs to be started might happen at the same cpu cycle (remember vic being 8mhz) The instruction isn't just stopped or temporarily halted, it's aborted, retired, and then restarted after the badline. At least afaik.
Or might there be some kind of clock-stretch going on?
As for delayed internal register update, VIC-II most likely isn't 8 MHz throughout, and i'm fairly certain the bus and register access circuitry is clocked at no more than 2 Mhz (and maybe only 1 for the latter). Also why can't the register update be delayed by a higher-priority bus access like DMA? :) |
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