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Forums > C64 Coding > GCR decoding on the fly
2013-03-31 12:46
lft

Registered: Jul 2007
Posts: 369
GCR decoding on the fly

Here's how to do it:

http://linusakesson.net/programming/gcr-decoding/index.php
 
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2013-04-25 20:56
Krill

Registered: Apr 2002
Posts: 2325
Quoting tlr
Do you have anything to back that timing suspicion up?
I can't see how the bit timing could be different all the way out to the port pins. Surely there must be at least one pipe line step through the VIA so even if there is a difference in timing on the bus out from the 6502 it will be reclocked.
No, hence my doubting my doubts. Probably there is no such problem if the SAX opcode itself works. That it doesn't with some drives may be the main problem to consider here.
2013-04-25 21:00
Krill

Registered: Apr 2002
Posts: 2325
Quote: also MiST from visual6502 actually did all the tests in a 1541 - with no sign of special behaviour.

Original MOS 6502, yes. I have no idea about the clones floating around, if they use the original circuitry and whatnot. After all, SAX does not work on that Synertec variant. But i haven't checked if this is somehow connected with it not being NMOS or anything, IF it isn't..
2013-04-26 18:53
Groepaz

Registered: Dec 2001
Posts: 10371
i'd just ignore that drive then, really :)
2013-04-26 19:37
JackAsser

Registered: Jun 2002
Posts: 1911
Quote: i'd just ignore that drive then, really :)

Ignore HCL's drive?!? Now that's bold... ;)
2013-04-26 20:23
HCL

Registered: Feb 2003
Posts: 698
OK, then i'll ignore all c128dcr drives.. ..and this means WAAAAR!!!

;)
2013-04-26 20:48
Groepaz

Registered: Dec 2001
Posts: 10371
every good irq handler has an inc $d030 in it =)
2013-06-23 20:43
doynax
Account closed

Registered: Oct 2004
Posts: 212
I've been testing the 16-cycle RMW ATN acknowledgment scheme discussed above and have run into a bit of trouble. It appears to work fine on my working (1571) drive, 1541U, VICE and Hoxs64. However the reaction is occasionally a cycle late in CCS64.

Anyway, I've isolated the issue into a little timing test comparing ASL $DD00 to ASL+STA $DD00.

I'd much appreciate it if anyone else would run these on hardware to compare the RMW/WR cases, confirm whether this is a known bug, or spot the error in my thinking.

https://sites.google.com/site/doynax/iec_repro.zip
2013-06-24 18:10
tlr

Registered: Sep 2003
Posts: 1586
Quote: I've been testing the 16-cycle RMW ATN acknowledgment scheme discussed above and have run into a bit of trouble. It appears to work fine on my working (1571) drive, 1541U, VICE and Hoxs64. However the reaction is occasionally a cycle late in CCS64.

Anyway, I've isolated the issue into a little timing test comparing ASL $DD00 to ASL+STA $DD00.

I'd much appreciate it if anyone else would run these on hardware to compare the RMW/WR cases, confirm whether this is a known bug, or spot the error in my thinking.

https://sites.google.com/site/doynax/iec_repro.zip


didn't examine it in detail but the asl $dd00 will shift CLKin into DATAout (=DATA out from the c64 will be the inverse of the state of the CLK line).

Maybe that is what bites you?
2013-06-24 18:34
doynax
Account closed

Registered: Oct 2004
Posts: 212
Quoting tlr
didn't examine it in detail but the asl $dd00 will shift CLKin into DATAout (=DATA out from the c64 will be the inverse of the state of the CLK line).

Maybe that is what bites you?
Good idea. That's thinking outside of the box.

Unfortunately I think you've got the shift direction mixed up. The CLK input is bit 6 with DATA out in bit 5 just below it, so an ASL should not pick up the two significant input bits.
2013-06-24 19:07
tlr

Registered: Sep 2003
Posts: 1586
Quoting doynax
Unfortunately I think you've got the shift direction mixed up. The CLK input is bit 6 with DATA out in bit 5 just below it, so an ASL should not pick up the two significant input bits.

Doh! :)
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