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Frantic
Registered: Mar 2003
Posts: 1627 |
Configurable addresses in multi sid tunes please
Hi guys!
If you want to make a fellow scener a tiny bit happier than he already is:
In multi sid tunes (2 sid chips or more) it would be super nice if more people started to add the possibility to configure the adress of the extra sid chips before the tune starts playing. After all, if you play multi sid tunes on a real machine it may not be easy to change the addressing of the extra sids you have. Sometimes there are jumpers which allow a bit of configuration (such as switching between de00 and df00, or between d4xx/d5xx or something). However, in many cases the configuration options are limited. For example, in my 3sid-machine, the sid chips are located at $d400, $d420 and $d500 and that's that. I can't change it. No jumpers or stuff like that. :)
I understand that most people use VICE or various cross platform music editors, or emulated+configurable "sid chips" like the ones in the 1541U2, when they deal with multi sid stuff, but still.. the real machine with real hardware sid chips is always the main target, right? ;)
Thanks in advance! ;) |
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Krill
Registered: Apr 2002
Posts: 2825 |
I wonder if the burden of support should really be on the software in this case. The hardware in question is optional add-on stuff, after all, pretty much a moving target.
Having the register layout be configurable seems more sensible, and should not be all that difficult with today's hardware.
Even nicer if we could agree on some standard to tell hardware about required/optional number of SIDs, register layout, panning etc. =) |
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chatGPZ
Registered: Dec 2001
Posts: 11101 |
check https://sourceforge.net/p/vice-emu/code/HEAD/tree/testprogs/SID.. and https://sourceforge.net/p/vice-emu/code/HEAD/tree/testprogs/SID.. |
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Frantic
Registered: Mar 2003
Posts: 1627 |
In my experience, TLR's routine (the first of the two links posted by Gpz above) works really well to detect the location of multiple SID chips and whether they are 6581 or 8580. Of course it is optional if someone wants to bear the burden of implementing this in their SID player code, to facilitate life for those of us who do have hardware for additional SID chips that does not allow configuration of base addresses, or that only allows limited configuration of base addresses. |
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Krill
Registered: Apr 2002
Posts: 2825 |
Semi-off topic, so bear with me for a moment. =)
With 32 (29) register slots per SID, more than 8 SIDs become somewhat cumbersome to address from software.
With configurable register layouts in mind, how feasible would be an addressing scheme that would, e.g., group all SIDs' registers together like so:$d400..$d41f: voice 1 frequency lo
$d420..$d43f: voice 1 frequency hi
[...]
$d780..$d79f: voice 3 envelope state (register 28=$1c) Never mind how sensible having 32 SIDs actually is, but black MIDI and the Furby organ exist, so... =) |
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chatGPZ
Registered: Dec 2001
Posts: 11101 |
that would require a whole lot of logic to decode and generate the chip select etc. could be a fun project to build for some TTL fetishist =) |
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Krill
Registered: Apr 2002
Posts: 2825 |
Quoting Groepazthat would require a whole lot of logic to decode and generate the chip select etc. could be a fun project to build for some TTL fetishist =) I thought that "configurable register layout" would already suggest using a CPLD or so. Discrete logic for that would be pretty hardcore indeed. =D
And then this isn't limited to discrete (or even physical) SIDs either. =) |
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chatGPZ
Registered: Dec 2001
Posts: 11101 |
not sure what you mean with "configurable" ... like, having an option to change the mapping via some extra registers? that would then require a helluva lots more logic too - cpld (or fpga) or not :) |
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Krill
Registered: Apr 2002
Posts: 2825 |
Quoting Groepaznot sure what you mean with "configurable" ... like, having an option to change the mapping via some extra registers? that would then require a helluva lots more logic too - cpld (or fpga) or not :) Yes, that. Doesn't seem more complex than other designs for C-64 add-ons implemented via CPLD/FPGA, though. =) (The actual logic, that is. Routing physical lines etc... different problem. =D) |
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tlr
Registered: Sep 2003
Posts: 1703 |
Quote: that would require a whole lot of logic to decode and generate the chip select etc. could be a fun project to build for some TTL fetishist =)
Not too difficult. Let the address bus of the SIDs be connected to A5-A9 instead of A0-A4, then generate the chip selects using a TTL decoder. Use for example four 74LS138s (1 of 8) or two 74LS154s (1 of 16).
Configurable, much trickier. :) |
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Krill
Registered: Apr 2002
Posts: 2825 |
Ok, but i was mostly aiming at feasibility of the layout when addressing registers via software, in a multi-SID player routine.
Also what about grouping in a voice-oriented way, such that there would be no offset of 7 between closely related registers for each of the 3 voices of a single SID, but an offset of 1 for all 3*N addressable voices. =D |
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