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oziphantom
Registered: Oct 2014
Posts: 478 |
EF3 boot/reset VHDL
I'm playing around with the EF3, but I can't get it to boot in a simulation.
I set the expansion port reset line to 'H' or 'Z' but the EF3 cart still holds it '0' or 'U' depending if I have it in Behavioral simulation or Post-Fit. There are also a lot of 'X' signals.
Does anybody know how it is suppose to boot? |
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oziphantom
Registered: Oct 2014
Posts: 478 |
setting all 3 buttons to '0' then waiting 100ns then '1' then waiting for a bit again and setting them to 0. Causes the cart to boot in the simulation. But is it real?
Sure Groepaz the circuit exists to de-bounce the buttons, but does it also cause an unintended delay at boot? |
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tlr
Registered: Sep 2003
Posts: 1714 |
Don't forget that 'U' isn't something appearing in real life so the three counter bits in reset_generator will have some (valid) initial state.
For Xilinx FPGA technologies a flop with a set input is defined to be synthesized as having the initial state of '1'. I'm assuming this applies to their CPLDs as well.
Judging from the lack of a testbench in the original design I'm guessing it was mostly verified on hardware and not in simulation. You could try adding the initial value of "111" to the counter and see what happens. |
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oziphantom
Registered: Oct 2014
Posts: 478 |
removing the button state toggling, and setting the counter to am initial state. Does have somethings ok, reset goes to 'Z' for example. But there are still a pile of 'X' and game which is a critical line in the boot process is 'U' so while it might be '0' it is something that needs to be 100% '0' for the cart to boot.
I was also thinking it might be a case of "well in the real world there will be delays between these signals internally so it works fine thanks to them".. |
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Trasher
Registered: Sep 2009
Posts: 8 |
Quote: Ok, I personally never use 'H' so I'm not entierly sure what happens. I would probably use 'Z' if I ment pulled up.
That aside you have some signals that are declared as inputs on the ef3 component, but assigned 'H' in your stimulus, e.g ba and n_roml, n_romh to name a few. Maybe this messes things up?
Without looking at the schematic I can see the ef3 component has a memory bus (mem_addr, mem_data) that you just left floating. Maybe it reads stuff from there in which case you would get 'U'/'X'?
You basically need to add some behavioural models for the relevant components connected to the vhdl design like memories and any logic that is there.
There is probably much more to it but that what I see at a glance.
If you have a pull-up; H is what you should use to mimic the actual pull-up resistor.
Did not look elsewhere than in what is posted in this thread, but having the *rom* signals as INPUT only also caught my eye. In reality they must be INOUT. I prefer to model things correctly, though it may not matter for this case. |
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oziphantom
Registered: Oct 2014
Posts: 478 |
By the ROM lines, you mean ROML and ROMH? Why would they need to be an input on the EF3? |
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tlr
Registered: Sep 2003
Posts: 1714 |
Quote: If you have a pull-up; H is what you should use to mimic the actual pull-up resistor.
Did not look elsewhere than in what is posted in this thread, but having the *rom* signals as INPUT only also caught my eye. In reality they must be INOUT. I prefer to model things correctly, though it may not matter for this case.
Pardon my ignorance, but as I've not used 'H' and 'L' in simulation I have to ask:
What is the result of:signal a : std_logic := 'H';
signal b : boolean;
...
b <= (a = '1');
... Will that resolve as true then? If not it will be a problem unless the code is specifically written to handle cases like that. |
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oziphantom
Registered: Oct 2014
Posts: 478 |
a quick google turns up : No
'1' != 'H'
you need to do a ?= '1' see https://books.google.com.au/books?id=iskV16bpYdgC&pg=PA49&lpg=P.. |
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tlr
Registered: Sep 2003
Posts: 1714 |
Quote: a quick google turns up : No
'1' != 'H'
you need to do a ?= '1' see https://books.google.com.au/books?id=iskV16bpYdgC&pg=PA49&lpg=P..
If that is the case, you can't just feed anything other than '0' or '1' into something not specifically designed to model that hw behaviour.
We concluded earlier that the code seems written mainly for synthesis into a CPLD implementation, which is reasonable IMO.
Check the condition for ba in freezer.vhdl as an example of a potentially problematic construct.
EDIT: sorry, ba should be fine as it is and:ed. You'll have to look around for ifs. |
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oziphantom
Registered: Oct 2014
Posts: 478 |
thinking about it 'Z' has just the same flaw. So setting it to 'H' or 'Z' is still going to make an ='1' and ='0' fail. |
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tlr
Registered: Sep 2003
Posts: 1714 |
Quote: thinking about it 'Z' has just the same flaw. So setting it to 'H' or 'Z' is still going to make an ='1' and ='0' fail.
Yes. Anything other than '1' or '0' needs some kind of handling in the implementation. For inout ports it's reasonable to expect it is handled but maybe not for pure ins. |
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