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JackAsser
Registered: Jun 2002
Posts: 2014 |
NMI delay
How much is an NMI delayed if triggered during IRQ-setup? |
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chatGPZ
Registered: Dec 2001
Posts: 11293 |
start here:
https://web.archive.org/web/20141224041136/http://visual6502.or..
You'll be more confused than before :o) |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: start here:
https://web.archive.org/web/20141224041136/http://visual6502.or..
You'll be more confused than before :o)
Haha, already did. Hence the question here. :D |
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chatGPZ
Registered: Dec 2001
Posts: 11293 |
also
https://web.archive.org/web/20210405071346/http://visual6502.or..
https://web.archive.org/web/20210405071501/http://visual6502.or.. |
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Fungus
Registered: Sep 2002
Posts: 668 |
Ah I see what you mean now, I'm not entirely sure either. |
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Krill
Registered: Apr 2002
Posts: 2940 |
Quoting JackAsserImagine u have a raster IRQ, and when the CPU performs the IRQ-load (i.e. push status, return address, read IRQ vector and jump (7c) ) an NMI occurs. This NMI will get delayed by that IRQ process, but how much at most? In VICE it looks like around 3-4 cycles, but I don't understand why. Why not 7c? Hazarding a guess, this seems rather analogous to the BA/AEC-goes-low VIC-takes-over-the-bus case (or REU DMA, for that matter).
Up to 3 write cycles (6502/6510 never needs more in a row, with any kind of interrupt being the worst case), then interruption, because it's safe only now.
Wouldn't be surprised if the NMI-on-top-of-IRQ and BA/AEC-low cases share some considerable assumptions, logic and circuitry. |
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Martin Piper
Registered: Nov 2007
Posts: 699 |
To really get an answer to this the PLA ROM needs to be understood.
http://www.visual6502.org/JSSim/expert.html
https://www.pagetable.com/?p=410
https://www.pagetable.com/?p=39
"At the end of each instruction, the PLA causes the T bitfield to reset, so that the next instruction starts with T1=1 again."
"All interrupt and NMI requests are always delayed until the current instruction is finished, i.e. until T gets reset." |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: To really get an answer to this the PLA ROM needs to be understood.
http://www.visual6502.org/JSSim/expert.html
https://www.pagetable.com/?p=410
https://www.pagetable.com/?p=39
"At the end of each instruction, the PLA causes the T bitfield to reset, so that the next instruction starts with T1=1 again."
"All interrupt and NMI requests are always delayed until the current instruction is finished, i.e. until T gets reset."
Given that and given that an IRQ really is a BRK-instruction under the hood we can assume the delay can be up to 7 cycles then? |
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chatGPZ
Registered: Dec 2001
Posts: 11293 |
If only it was that simple :o)
It might be a good idea to simulate and iterate too all possible timings (ie trigger the nmi in every possible half cycle of that "BRK") and then see what happens. If i understood the wiki correctly, there are still special cases to consider. |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: If only it was that simple :o)
It might be a good idea to simulate and iterate too all possible timings (ie trigger the nmi in every possible half cycle of that "BRK") and then see what happens. If i understood the wiki correctly, there are still special cases to consider.
Yeah, someday. For now I simply made sure that my IRQs never collides with the NMIs. :) |
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chatGPZ
Registered: Dec 2001
Posts: 11293 |
BAH! DO IT! :D |
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