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JackAsser
Registered: Jun 2002
Posts: 2014 |
NMI delay
How much is an NMI delayed if triggered during IRQ-setup? |
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Fungus
Registered: Sep 2002
Posts: 668 |
1 cycle I think?
Was talking to groepaz a couple months ago about "eaten IRQs" which is a bug in the 6502. I supposed if the NMI came at the wrong time after an IRQ the IRQ can be lost, or a BRK.
There was some talk about it on the 6502 site he linked. |
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chatGPZ
Registered: Dec 2001
Posts: 11293 |
what do you mean "during IRQ-setup"? |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: 1 cycle I think?
Was talking to groepaz a couple months ago about "eaten IRQs" which is a bug in the 6502. I supposed if the NMI came at the wrong time after an IRQ the IRQ can be lost, or a BRK.
There was some talk about it on the 6502 site he linked.
In VICE it's definetly more than 1 cycle, but hard to tell. |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: what do you mean "during IRQ-setup"?
When the CPU performs the 7-cycle IRQ-setup (i.e. push status etc on the stack). During that time NMIs won't interrupt and will be delayed. But it doesn't seem to be delayed the full 7 cycles (at least not in VICE, havn't tested on the real thing but this is surely emulated correctly anyways). |
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chatGPZ
Registered: Dec 2001
Posts: 11293 |
ok. for that case, basically look at it like your NMI interrupts a BRK instruction (because it IS a BRK instruction!).
and then to see the details, simulate in visual6502 :) i am still struggling at explaining this properly, it should be added to NMS :) |
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Oswald
Registered: Apr 2002
Posts: 5076 |
cool, this sounds like a yummy raster fx :) |
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Fungus
Registered: Sep 2002
Posts: 668 |
Oh you mean the lockout time before another NMI can occur, isn't it the instruction length, but... if NMI is held low then another one shouldn't be able to strike unless you are doing something weird. Are you using the CIA where the code is executed the so the flag is cleared automatically? That would present a problem. |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: ok. for that case, basically look at it like your NMI interrupts a BRK instruction (because it IS a BRK instruction!).
and then to see the details, simulate in visual6502 :) i am still struggling at explaining this properly, it should be added to NMS :)
Struggling also (and already checked visual6502), hence I took the lazy path and just asked. :D |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: Oh you mean the lockout time before another NMI can occur, isn't it the instruction length, but... if NMI is held low then another one shouldn't be able to strike unless you are doing something weird. Are you using the CIA where the code is executed the so the flag is cleared automatically? That would present a problem.
No no no not at all. Imagine u have a raster IRQ, and when the CPU performs the IRQ-load (i.e. push status, return address, read IRQ vector and jump (7c) ) an NMI occurs. This NMI will get delayed by that IRQ process, but how much at most? In VICE it looks like around 3-4 cycles, but I don't understand why. Why not 7c? |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: cool, this sounds like a yummy raster fx :)
It depends on the max delay, hence my question. :D |
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