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JackAsser
Registered: Jun 2002
Posts: 2014 |
NMI delay
How much is an NMI delayed if triggered during IRQ-setup? |
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Martin Piper
Registered: Nov 2007
Posts: 699 |
https://en.wikipedia.org/wiki/Programmable_logic_array
"the original 6502 chip contained a PLA"
It's obviously not a full ROM. |
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chatGPZ
Registered: Dec 2001
Posts: 11293 |
That's simply wrong. It's a decode ROM, no more, no less. (And yes, what Krill said. Its not a traditional ROM, sure. Its a logic array. And that kind of thing is usually called decode ROM - not PLA. PLA is programmable, not mask edited.) |
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Martin Piper
Registered: Nov 2007
Posts: 699 |
Quote: That's simply wrong. It's a decode ROM, no more, no less. (And yes, what Krill said. Its not a traditional ROM, sure. Its a logic array. And that kind of thing is usually called decode ROM - not PLA. PLA is programmable, not mask edited.)
Wrong. The PLA in the 6502 is sparse. A full ROM maps every single output. The 6502 PLA saves space compared to a full ROM.
It's why we have illegal opcodes.
https://www.pagetable.com/?p=39 |
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chatGPZ
Registered: Dec 2001
Posts: 11293 |
You don't have to copypaste me the ill informed stuff that you found on reddit.
FPLA is a synonym for the (modern) FPGA btw - and has zero to do with the oldschool "PLA".
(yes, please inform me about how illegal opcodes work, i always wanted to know) |
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Martin Piper
Registered: Nov 2007
Posts: 699 |
Quote: You don't have to copypaste me the ill informed stuff that you found on reddit.
FPLA is a synonym for the (modern) FPGA btw - and has zero to do with the oldschool "PLA".
(yes, please inform me about how illegal opcodes work, i always wanted to know)
Wrong again.
Look at the chip layout, it's obviously a PLA, not a full ROM.
http://www.visual6502.org/JSSim/expert.html?nosim=t&panx=110.5&.. |
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Martin Piper
Registered: Nov 2007
Posts: 699 |
"approximately top fifth of the chip (with the regular rectangular pattern) is the **PLA** that decodes instructions."
https://www.righto.com/2013/01/a-small-part-of-6502-chip-explai..
Basically "paz" you're not considering the actual layout of the gates on the chip and instead applying your incorrect thinking from an incorrect understanding about some higher level context which isn't appropriate. |
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Martin Piper
Registered: Nov 2007
Posts: 699 |
This explains why your PLA explanation is wrong "paz".
https://en.wikipedia.org/wiki/Programmable_logic_array
"In 1970, Texas Instruments developed a *mask-programmable IC*..." "...TI coined the term **Programmable Logic Array** for this device." |
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chatGPZ
Registered: Dec 2001
Posts: 11293 |
If you'd spend as much time programming as googling up your "knowledge", perhaps your verlet integration code would even be ready by now :) |
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Fungus
Registered: Sep 2002
Posts: 668 |
Martin, if you have nothing to add to this conversation, then kindly shut up. No one wants to argue with you about tangential subjects just so you can die on yet another hill about something you clearly misunderstand.
Good lord man... |
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Martin Piper
Registered: Nov 2007
Posts: 699 |
Quote: If you'd spend as much time programming as googling up your "knowledge", perhaps your verlet integration code would even be ready by now :)
We can see when you're wrong when you go into irrelevant topics. |
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