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AKA :
NMOS 6510 Unintended Opcodes
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Pokefinder.org
User Comment Submitted by chatGPZ on 22 January 2016
all the test programs are in the VICE testprograms repo.
also a new/updated version is here: No More Secrets v0.9 | User Comment Submitted by JAC on 22 January 2016
Thanks! And I finally realized the pun with the title - brilliant. Would be great to have the test-sources available. | User Comment Submitted by Kabuto on 18 October 2015
This also misses out on a potential use case for ANE / LAX #imm: according to the formulas these should be perfectly stable if the A register previously contained $ff, thus:
lda #$ff
ane #value
would be equivalent to:
txa
and #value
and:
lda #$ff
lax #value
would be equivalent to:
lda #value
ldx #value
So these might be actually useful if A happens to contain the value $ff.
Or, more generalized, these are safe if all bits that could be 0 in A are 0 in the immediate value for LAX imm or in either the immediate value or X or both for ANE. | User Comment Submitted by Kabuto on 18 October 2015
This is a nice summary, however lacking a few tidbits:
As mentioned, VIC DMA pausing SH*/TAS/LAS opcodes can change their behaviour.
I did some hardware tests on my C64 - in my case, if there was no DMA, these were perfectly stable, no matter whether or not a page was crossed.
DMA changed behaviour if it kicked in for the read cycle directly before the write cycle (but, IIRC, also perfectly stable). The CPU still uses the faulty address in case of overflow but no longer ANDs the value to be written with ((address >> 8) + 1). | User Comment Submitted by Karoshier on 12 January 2015
Very nice reading. Thanks for sharing it!
IMHO this should be somehow added to Codebase64 in base:6502_6510_coding. Maybe as a link into the books section? | User Comment Submitted by chatGPZ on 29 December 2014
the only issue you found there is that it should be "one half <b>of</b> each cycle".
and yes, it describes exactly what is happening in the CPU. and this document is not for you, apparently. | User Comment Submitted by Oswald on 29 December 2014
great work here, but I found some issues:
1. "experienced programmers (SUCH AS MYSELF)". this part should've been left out leave your ego at home.
2. SAX: half cycles? there's no such thing! imho simply both mechanism activates at the SAME time. how could the cpu run faster than the clock dictates ?! and how the AND works in here is explained quite weirdly. there are NO read enable signals allowing 1's and 0's to be this or that, from what I know its simpy NMOS behaviour that when two voltages 'collide' this will happen.
frankly I was hoping it would describe stuff on the cpu inner level. | User Comment Submitted by Zyron on 29 December 2014 User Comment Submitted by alwyz on 29 December 2014 User Comment Submitted by Conjuror on 26 December 2014
Best Christmas present this year. Thanks for putting it all together like this. | User Comment Submitted by Six on 26 December 2014
What an awesome read! Thanks for this! | User Comment Submitted by 6R6 on 25 December 2014
Thanks! Nice reading material on xmas eve. :) | User Comment Submitted by Bitbreaker on 25 December 2014
Lügenpresse! Lügenpresse! :-P | User Comment Submitted by Bamse on 25 December 2014 User Comment Submitted by plagueis on 25 December 2014
What an Uber excellent release! This is what it's all about here. Even an often insulting, arrogant, rude person like Groepaz had the integrity to release what looks to be a very thorough treatise on a worthy and interesting subject. Thanks! And I really mean it. It was written for highly experienced coders such as himself he says near the beginning :) Happy Holidays to Groepaz and all!!! | User Comment Submitted by Knut Clausen on 24 December 2014
Now I know what I'll be reading this christmas. Thanks! | User Comment Submitted by E$G on 24 December 2014
excellent present for xmas! | User Comment Submitted by Axis/Oxyron on 24 December 2014
Wow, this looks really interesting. Will be the first thing on my TODO list when I return from my journey into 68k. |
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