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Cycle Jitter TestProg [2015] |
AKA :
force_cycle
| User rating: | awaiting 8 votes (8 left) |
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Production Info
Submitted by Copyfault on 27 July 2015
Old cycle jitter test prog allowing to force a raster irq condition to occur on a selected processing cycle. The current jitter value (=delay till start of irq routine [#cycles]) is printed on the text screen.
Basically the main code consists of the loop
.loop INC $C000,X
BPL .loop
BMI .loop
For different jitter values you can change the following settings (adjust Source Code accordingly):
;-------------------------------------
; Meta Settings
;-------------------------------------
TAKE_BPL
-> Set to '1' for ensure that the first branch-instruction "BPL" is taken
MEM_MISALIGN
-> This is the no. of bytes the test code loop will be shifted _below_ $0b00 to configure different page crossing situations for the branch instructions (formula is CODE_ADRESS = $0b00 - MEM_MISALIGN)
Reasonable values are
0: no page break
1: page_break for both branch instructions
4: page_break for BMI and BPL (if taken)
5: page_break for BMI (if taken), for BPL !if not taken!
6: page_break for BMI but not for BPL
COND_CYCLE
-> Use this to set the cycle no. of the irq condition
cycle 0 is the first INC_cycle, increment this value to let the irq occur at a later cycle
For ex., COND_CYCLE=8 (-> irq occurs on 2nd bpl-cycle) gives the "worst case" jitter of '7' iff branch is taken
This test prog shows that there are eight different jitter values (0,1,...,7) possible even when no unintended opcodes are used. |
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