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JackAsser
Registered: Jun 2002
Posts: 2038 |
NMI delay
How much is an NMI delayed if triggered during IRQ-setup? |
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Martin Piper
Registered: Nov 2007
Posts: 739 |
To really get an answer to this the PLA ROM needs to be understood.
http://www.visual6502.org/JSSim/expert.html
https://www.pagetable.com/?p=410
https://www.pagetable.com/?p=39
"At the end of each instruction, the PLA causes the T bitfield to reset, so that the next instruction starts with T1=1 again."
"All interrupt and NMI requests are always delayed until the current instruction is finished, i.e. until T gets reset." |
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JackAsser
Registered: Jun 2002
Posts: 2038 |
Quote: To really get an answer to this the PLA ROM needs to be understood.
http://www.visual6502.org/JSSim/expert.html
https://www.pagetable.com/?p=410
https://www.pagetable.com/?p=39
"At the end of each instruction, the PLA causes the T bitfield to reset, so that the next instruction starts with T1=1 again."
"All interrupt and NMI requests are always delayed until the current instruction is finished, i.e. until T gets reset."
Given that and given that an IRQ really is a BRK-instruction under the hood we can assume the delay can be up to 7 cycles then? |
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chatGPZ
Registered: Dec 2001
Posts: 11523 |
If only it was that simple :o)
It might be a good idea to simulate and iterate too all possible timings (ie trigger the nmi in every possible half cycle of that "BRK") and then see what happens. If i understood the wiki correctly, there are still special cases to consider. |
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JackAsser
Registered: Jun 2002
Posts: 2038 |
Quote: If only it was that simple :o)
It might be a good idea to simulate and iterate too all possible timings (ie trigger the nmi in every possible half cycle of that "BRK") and then see what happens. If i understood the wiki correctly, there are still special cases to consider.
Yeah, someday. For now I simply made sure that my IRQs never collides with the NMIs. :) |
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chatGPZ
Registered: Dec 2001
Posts: 11523 |
BAH! DO IT! :D |
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Martin Piper
Registered: Nov 2007
Posts: 739 |
Quote: Yeah, someday. For now I simply made sure that my IRQs never collides with the NMIs. :)
There's no real problem as both will trigger eventually. |
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chatGPZ
Registered: Dec 2001
Posts: 11523 |
The problem is having predictable timing in all cases. Of course they trigger (except when they don't - see the wiki pages). |
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JackAsser
Registered: Jun 2002
Posts: 2038 |
Quote: The problem is having predictable timing in all cases. Of course they trigger (except when they don't - see the wiki pages).
Exactly. My NMIs must NOT be delayed or this card house will fall completly and ungraceful. |
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Fungus
Registered: Sep 2002
Posts: 751 |
Quote: The problem is having predictable timing in all cases. Of course they trigger (except when they don't - see the wiki pages).
Yes this is what I was looking at too, to see in which instances the IRQ is "eaten". I need to do some simulations there too and see if this behavior can be documented so we know exactly when and how this can occur.
I was already aware of BRK can eat an IRQ and vice versa, but if NMI is also a BRK instruction then the same thing could happen. It's just a matter of under what circumstances... |
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chatGPZ
Registered: Dec 2001
Posts: 11523 |
Yes. Those wiki pages are very confusing for that matter, because they also consider cases that can never happen - in a C64 anyway. |
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