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chatGPZ
Registered: Dec 2001
Posts: 11116 |
useless opcodes riddle - wtf is up with LAS and TAS?
Due to my emulator related activities in the last year(s) i digged more into the so called "illegal" opcodes, and the result is a nice (hopefully) PDF that i'll publish soonish (when some of you lazy bastards are done proofreading =D) - which includes complete state of the art reference to all of these, plus a bunch of real world examples on how to use these (sometimes very weird behaving) instructions... (in large part provided by bitbreaker, thumbs up!) Its about time for a comprehensive document on this topic that is suitable for normal people =)
however, two opcodes seem to be completely useless and so far i cant think of what to use them for in real world code:
- LAS abs,y ($BB) (A,X,SP = addr & SP)
- TAS abs,y ($9B) (SP = A & X ; addr = SP & addrhi+1)
if any of you have used these before, or for whatever reason have an idea on what to do with them - let me know please, this is your chance to earn some karma upgrade points :o)
(and as a sidenote, some not so obvious *short* snippets that are using SLO, RLA, RRA or ISC are welcome too)
let's bust some more myths! |
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CRT
Registered: Oct 2012
Posts: 87 |
I have had fun with the same thoughts. It resulted in a challenge for myself to one day use TAS for something. Still failing but I'm sure a thread like this will come up with something.
AND X register with accumulator and store result in stack
pointer, then AND stack pointer with the high byte of the
target address of the argument + 1. Store result in memory. |
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The Phantom
Registered: Jan 2004
Posts: 360 |
I recall FOE releasing a messy about undocumented opcodes, perhaps they'll help in your PDF?
Undocumented Opcodes
If not, didn't mean to waste your time, and look forward to the PDF :) |
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Peiselulli
Registered: Oct 2006
Posts: 81 |
For ISC, here is a real world example (discussion in german)
http://www.forum64.de/wbb3/board2-c64-alles-rund-um-den-brotkas.. |
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soci
Registered: Sep 2003
Posts: 473 |
Here's a real world example from IDEDOS for using SLO:
; A is zero before reaching here
.if R65C02
.9719 06 8e asl $8e asl next_sector+3
.971b 26 8d rol $8d rol next_sector+(2, 1, 0,)
.971d 26 8c rol $8c
.971f 26 8b rol $8b
.9721 a5 8e lda $8e lda next_sector+3
.else
.973b 07 8e slo $8e slo next_sector+3
.973d 26 8d rol $8d rol next_sector+(2, 1, 0,)
.973f 26 8c rol $8c
.9741 26 8b rol $8b
.fi
It spares 2 bytes for leaving out the last LDA when using illegal opcodes ;) |
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soci
Registered: Sep 2003
Posts: 473 |
Another one from IDEDOS for using ISB (ISC):
; A is zero and C=0 before reaching here
.elsif R65C02
.a77e fe 1e 19 inc $191e,x inc buffer_address_hi_exp,x
.a781 bd 1e 19 lda $191e,x lda buffer_address_hi_exp,x
.else
.a792 ff 1e 19 isb $191e,x isb buffer_address_hi_exp,x
.a795 49 ff eor #$ff eor #$ff
.fi
Spares a byte and is faster ;) |
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Hein
Registered: Apr 2004
Posts: 933 |
No LAS or TAS, but ARR.
To check if the target note frequency has been reached for a 'glide to' function:
;x=$0e,$07,$00
ldy v1_note_target,x ;target note
lda freq_table_lo,y
sec
sbc v1_freq_lo_buffer,x
sta zp_idx_lo
lda freq_table_hi,y
sbc v1_freq_hi_buffer,x
sta zp_idx_hi
ldy v1_note_base,x ;start note
lda freq_table_lo,y
cmp zp_idx_lo
lda freq_table_hi,y
sbc zp_idx_hi
arr #$80
eor v1_porta_lfo_length,x ;bit7 = 0 if glide up, bit7 = 1 if glide down
bpl set_calculated_note ;still not reached
[edit] Ah, you're asking for RRA, not ARR.. :) Only used RRA (lo),y to have a short opcode for cycle wasting.. [/edit] |
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doynax
Account closed
Registered: Oct 2004
Posts: 212 |
To my shame I must confess that I haven't found any use for LAS or TAS either.
You'd think TAS would be useful for clearing all of the registers and stack pointer during initialization but LXA #$00/TAY/TXS is a byte shorter, plus you probably want reset S to $FF anyway.
As for SLO/SRE I may have mentioned this before but below is the host side of a two-bit IRQ transfer running in 64 cycles per byte, including loop overhead. A asynchronous IRQ protocol works by toggling ATN, then waiting for the maximum delay period when the drive can be relied on to have the results back before sampling them and toggling ATN for the next bit pair.
By using the SLO/SRE RMW instructions we can both sample DATA/CLK and toggle ATN within two cycles inside the same instruction, instead of four as you would get with separate EOR/STA. ldy #%00000100
;Assert ATN
loop: arr #%11111010 ;cdab00--
arr #%11111010 ;dcdab00-
ror ;cdcdab00
sre $dd00-4,y ;cefdaB--
;Release ATN
sty $dd00
alr #%11111100 ;0cefdaB0
sta merge+1
slo $dd00 ;hcef1--0
;Assert ATN
and #%10000000 ;h0000000
merge: adc #%00000000 ;hcefdaBg
sta sector,x
sre $dd00-4,y ;0ab001--
;Release ATN
inx
sty $dd00
beq break
and #%01100000 ;0ab00000
slo $dd00 ;dab01---
bne loop ;(BRA) |
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lft
Registered: Jul 2007
Posts: 369 |
@doynax: Although it makes some assumptions about which vic bank is active, right? |
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Copyfault
Registered: Dec 2001
Posts: 466 |
Hey Groepaz,
Ninjas 6-Sprites-over-FLI-routine makes heavy use of SLO and RRA (maybe also RLA, not 100% sure), but I guess this example is already covered in the pdf ?!?
I've never used LAE/SHS ($bb/$9b) up to now. As you are looking for "real world examples" I guess that you completely found out what this "unstability" (which is usually connected to both opcodes) really means, right?
Looking forward to reading this paper;)
Bye-
CF |
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chatGPZ
Registered: Dec 2001
Posts: 11116 |
ninja contributed that routine, yes :) and yes, the instabilities are covered :) |
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