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chatGPZ
Registered: Dec 2001
Posts: 11136 |
(Ab)use of dummy accesses
For the next release of my "No more Secrets" doc i am preparing a chapter related to the dummy access which happen when the CPU performs an internal operation. Once again i am looking for some examples on how to (ab)use it :) I guess everyone knows "inc $d019" - but i am sure there is more than this. And not only with RMW instructions. So if you have anything in your mind - just drop it here!
here are some related notes which i pasted together. feel free to proofread and point out mistakes :) |
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Copyfault
Registered: Dec 2001
Posts: 466 |
Feeding data to the sprite pattern pipe for a sprite that is displayed "far out right" which did not have its DMA-cycles before comes to mind.
IIRC, the only way to get all three pattern bytes filled correctly you needed aSTA VIC_REG,x at the correct position in the rasterline, s.t. the 4th cycle occurs at the first sprite DMA-cycle and the 5th (the W-cycle) at the 2nd sprite DMA-cycle. This way, the sprite pattern byte was filled with byte read in 4th cycle from the (uncorrected!) VIC-adress | ghostbyte | byte stored in 5th cycle , so the internal operation cycle was mandatory to achieve this. |
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Compyx
Registered: Jan 2005
Posts: 631 |
Copyfault: are you talking about the 'x-stretch' effect you get with dysp's when the low-index sprites go too far into the right border? |
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chatGPZ
Registered: Dec 2001
Posts: 11136 |
Quote:The music routine from Fred Gray performs a read and write on IO
thats not abusing the dummy accesses though.... it relies on the floating bus value (what a terrible idea =P) |
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tlr
Registered: Sep 2003
Posts: 1723 |
Quote: Copyfault: are you talking about the 'x-stretch' effect you get with dysp's when the low-index sprites go too far into the right border?
It refers to the long mysterious $ff glitches usually appearing at the top of sprite #0 when moved far right (it appears for all sprites but most not visible). Those can be controlled by placing the right values on the internal vic-bus in two adjacent cycles.
There's a length discussion in a thread somewhere. |
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chatGPZ
Registered: Dec 2001
Posts: 11136 |
it would be great if you'd post an actual working example, that would safe a lot of time =) |
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tlr
Registered: Sep 2003
Posts: 1723 |
Quote: it would be great if you'd post an actual working example, that would safe a lot of time =)
Copyfault implemented that here: Sideborder Sprite Data Fetch TestProg, presumably based on my suggestion in post #12 of this thread: Sprite data fetch in sideborder |
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Copyfault
Registered: Dec 2001
Posts: 466 |
Sorry for not posting the links.
Thanks a bunch, tlr! And ofcourse, the basic idea for getting the pattern bytes at the right positions of the sprite data pipe was yours!!! |
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Fred
Registered: Feb 2003
Posts: 284 |
Quote: Quote:The music routine from Fred Gray performs a read and write on IO
thats not abusing the dummy accesses though.... it relies on the floating bus value (what a terrible idea =P)
The dummy write in the INC instruction is still executed but perhaps in this example has no audible impact on the output of the SID. The dummy access writes the same value to the SID again. I can imagine that when the gate bit was already set and with the INC instruction set again in the first write, that it will have impact on the ADSR state.
Also it will write 2 times to the SID with 1 cycle difference which is not possible with any other instruction. This cycle difference may be abused with any IO register.
Some example of my CIA test routine which makes use of the dummy access:
https://sourceforge.net/p/vice-emu/bugs/740/ |
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chatGPZ
Registered: Dec 2001
Posts: 11136 |
Ah yes, it would indeed introduce a small difference in timing. ok :) |
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chatGPZ
Registered: Dec 2001
Posts: 11136 |
come on coronapeoples, this cant be all! :) |
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