Text from Safe VSP
| Description: | Top scroller |
| Text: | TECHNICAL LOWDOWN: THE DREADED VSP CRASH IS CAUSED BY A METASTABILITY CONDITION IN THE DRAM. SOME HAVE SPECULATED THAT IT HAS TO DO WITH REFRESH CYCLES, BUT HOPEFULLY THE DETAILED EXPLANATION IN THIS SCROLLER WILL CRUSH THAT MYTH ONCE AND FOR ALL. BUT FIRST, THIS IS WHAT THE MACHINE BEHAVES LIKE FROM A PROGRAMMER'S POINT OF VIEW. LET US CALL MEMORY LOCATIONS ENDING IN 7 OR F FRAGILE. SOMETIMES WHEN VSP IS PERFORMED, SEVERAL FRAGILE MEMORY CELLS ARE RANDOMLY CORRUPTED ACCORDING TO THE FOLLOWING RULE: EACH BIT IN A FRAGILE MEMORY CELL MIGHT BE CHANGED INTO THE CORRESPONDING BIT OF ANOTHER FRAGILE CELL WITHIN THE SAME PAGE. THIS SPECIFIC BEHAVIOUR CAN BE EXPLOITED IN SEVERAL WAYS: ONE APPROACH IS TO ENSURE THAT EVERY FRAGILE BYTE IN A PAGE IS IDENTICAL. IF THE PAGE CONTAINS CODE, FOR INSTANCE, CORRUPTION IS AVOIDED IF ALL THE FRAGILE BYTES ARE $EA (NOP). SIMILARLY, IN FONT DEFINITIONS, THE BOTTOM LINE OF EACH CHARACTER COULD BE BLANK. ANOTHER TECHNIQUE IS TO SIMPLY AVOID ALL FRAGILE MEMORY LOCATIONS. THE UNDOCUMENTED OPCODE $80 (NOP IMMEDIATE) CAN BE USED TO SKIP THEM. DATA STRUCTURES CAN BE DESIGNED TO HAVE GAPS IN THE CRITICAL PLACES. THIS LATTER TECHNIQUE IS USED IN THIS DEMO, INCLUDING THE MUSIC PLAYER OF COURSE. DATA THAT CANNOT HAVE GAPS, I.E. GRAPHICS, IS CONTINUOUSLY RESTORED FROM SAFE COPIES ELSEWHERE IN MEMORY. YOU CAN USE SHIFT LOCK TO DISABLE THIS REPAIR, AND EVENTUALLY YOU SHOULD SEE GARBAGE ACCUMULATING ON THE SCREEN. AND YET THE CODE WILL KEEP RUNNING. THUS, FOR THE FIRST TIME, THE VSP CRASH HAS BEEN TAMED. NOW FOR THE EXPLANATION. THE C64 ACCESSES MEMORY TWICE IN EVERY CLOCK CYCLE. EACH MEMORY ACCESS BEGINS WITH THE LSB OF THE ADDRESS (ALSO KNOWN AS THE ROW ADDRESS) BEING PLACED ON AN INTERNAL BUS CONNECTED TO THE DRAM CHIPS. AS SOON AS THE ROW ADDRESS IS STABLE, THE ROW ADDRESS STROBE (RAS) SIGNAL IS GIVEN. EACH DRAM CHIP NOW LATCHES THE ROW ADDRESS INTO A REGISTER, AND THIS REGISTER CONTROLS A MULTIPLEXER WHICH CONNECTS THE SELECTED MEMORY ROW TO A SET OF WIRES CALLED SENSE LINES. EACH SENSE LINE CONNECTS TO A SINGLE BIT OF MEMORY. THE SENSE LINES HAVE BEEN PRECHARGED TO A VOLTAGE IN BETWEEN LOGICAL ZERO AND LOGICAL ONE. THE CHARGE STORED IN THE MEMORY CELL AFFECTS THE SENSE LINE TOWARDS A SLIGHTLY LOWER OR HIGHER VOLTAGE DEPENDING ON THE BIT VALUE. A FEEDBACK AMPLIFIER SENSES THE VOLTAGE DIFFERENCE AND EXAGGERATES IT, SO THAT THE SENSE LINE REACHES THE PROPER VOLTAGE REPRESENTING EITHER ZERO OR ONE. BECAUSE THE MEMORY CELL IS CONNECTED (THROUGH THE MULTIPLEXER) TO THE SENSE LINE, THE AMPLIFIED CHARGE WILL ALSO FLOW BACK AND REFRESH THE MEMORY CELL. HENCE, A MEMORY ROW IS REFRESHED WHENEVER IT IS OPENED. VSP IS ACHIEVED BY TRIGGERING A BADLINE CONDITION DURING IDLE MODE IN THE VISIBLE PART OF A RASTERLINE. WHEN THIS HAPPENS, THE VIC CHIP GETS CONFUSED ABOUT WHAT MEMORY ADDRESS TO ACCESS DURING THE HALF-CYCLE FOLLOWING THE WRITE TO $D011. IT SETS THE INTERNAL BUS LINES TO 11111111 IN PREPARATION FOR AN IDLE FETCH, BUT SUDDENLY CHANGES ITS MIND AND TRIES TO READ FROM AN ADDRESS WITH AN LSB OF 00000111. NOW, SINCE ELECTRICAL LINES CAN'T CHANGE VOLTAGE INSTANTANEOUSLY, THERE IS A BRIEF MOMENT OF TIME WHEN EACH OF THE CHANGING BITS (BIT 3 THROUGH 7) IS NEITHER A VALID ONE NOR A VALID ZERO. BUT BECAUSE THE VIC CHIP CHANGES THE ADDRESS AT AN ABNORMAL TIME, THERE IS NOW A RISK THAT THE RAS SIGNAL, WHICH IS GENERATED INDEPENDENTLY BY ANOTHER PART OF THE VIC CHIP, IS SENT WHILE ONE OR MORE BUS LINES IS WITHIN THE UNDEFINED VOLTAGE RANGE. WHEN AN UNDEFINED VOLTAGE IS LATCHED INTO A REGISTER, THE REGISTER ENTERS A METASTABLE STATE, WHICH MEANS THAT ITS OUTPUT WILL FLICKER RAPIDLY BETWEEN ZERO AND ONE SEVERAL TIMES BEFORE SETTLING. THIS HAS CATASTROPHIC CONSEQUENCES FOR A DRAM: THE ROW MULTIPLEXER WILL CONNECT SEVERAL DIFFERENT MEMORY ROWS, ONE AT A TIME, TO THE SAME SENSE LINES. BUT AS SOON AS SOME CHARGE HAS MOVED FROM A MEMORY CELL TO THE SENSE LINE, THE AMPLIFIER WILL PULL IT ALL THE WAY TO A ONE OR A ZERO. IF, AT THIS POINT, ANOTHER MEMORY ROW IS CONNECTED, THEN THE CHARGE WILL TRAVEL FROM THE SENSE LINE INTO THIS OTHER MEMORY CELL. IN SHORT, ONE MEMORY CELL GETS REFRESHED WITH THE BIT VALUE OF A DIFFERENT MEMORY CELL. NOTE THAT BECAUSE THE BUS LINES CHANGE FROM $FF TO $07, ONLY MEMORY ROWS WITH AN ADDRESS ENDING IN THREE ONES ARE AT RISK OF BEING OPENED SIMULTANEOUSLY. THIS EXPLAINS WHY CORRUPTION CAN ONLY OCCUR IN MEMORY LOCATIONS ENDING IN 7 OR F. FINALLY, THIS PHENOMENON HINGES ON THE EXACT TIMING OF THE RAS SIGNAL AT THE NANOSECOND LEVEL, AND ON MANY MACHINES THE CRITICAL SITUATION SIMPLY DOESN'T OCCUR. THE TIMING (AND THUS THE PROBABILITY OF A CRASH) DEPENDS ON FACTORS SUCH AS TEMPERATURE, VIC REVISION, PARASITIC CAPACITANCE AND RESISTANCE OF THE TRACES ON THE MOTHERBOARD, POWER SUPPLY RIPPLE AND INTERFERENCE WITH OTHER PARTS OF THE MACHINE SUCH AS THE PHASE OF THE COLOUR CARRIER WITH RESPECT TO THE DOTCLOCK. THE LATTER IS ASSIGNED RANDOMLY AT POWER-ON, BY THE WAY, WHICH COULD BE THE REASON WHY A POWER-CYCLE SOMETIMES HELPS. THIS IS LFT SIGNING OFF. |
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