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Monte Carlos
Registered: Jun 2004
Posts: 351 |
Left/Right Border switching in middle of rasterline
The last days i experimented a little with bit 3 of $d016. I had the brainfart to broaden the border on the left and keep it normal on the right. Disappointingly, this seems to work only in every non badline. If i try to switch bit 3 of $d016 during a badline i either get both left and right borders equal or i turn off the border completely for the next rasterline. Does somebody have an explanation in terms of internal VIC timing? I also tried modifying the timing with sprites or HSP to be able to write to $d016 in the correct cycle. |
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lft
Registered: Jul 2007
Posts: 369 |
Nope, then you want the vic to "miss" both occasions where the border might be turned on. So you reconfigure it during cycle 56. In your scenario, you want it to "hit" the first occasion. |
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Monte Carlos
Registered: Jun 2004
Posts: 351 |
So in cycle 55 DMA is still going on while in cycle 56 it's already over. That's why cpu can't access $d016 in cycle 55.
Perhaps one should try this with RamEx or SCPU? |
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chatGPZ
Registered: Dec 2001
Posts: 11111 |
that doesnt enable you to write to registers when a DMA is going on either :) |
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Monte Carlos
Registered: Jun 2004
Posts: 351 |
No, i meant using reu and dma transfer to $d016 |
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Oswald
Registered: Apr 2002
Posts: 5017 |
VICII will either read those 40 bytes on a badline or display garbage. guess which will happen with REU attached ?
btw why the fuck do anyone call that DMA ? its a total misuse of the term:
Direct Memory Access (DMA) is a capability provided by some computer bus architectures that allows data to be sent directly from an attached device (such as a disk drive) to the memory on the computer's motherboard. The microprocessor is freed from involvement with the data transfer, thus speeding up overall computer operation. |
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Rastah Bar
Registered: Oct 2012
Posts: 336 |
Maybe you could postpone the badline condition until after the left border edge? Then you may be able to change $d016 in the left border and change it back again after it. Then force a badline condition. This will mess with the graphics on the badlines, I suppose. (If I understand it correctly, this is VSP, isn't it?). |
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lft
Registered: Jul 2007
Posts: 369 |
Quoting Oswaldbtw why the fuck do anyone call that DMA ? its a total misuse of the term
It's correct usage of the term. DMA can also be in the direction from memory to peripheral (as in the case with the VIC accessing main memory without CPU involvement). I don't know why the definition you quoted says otherwise. |
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lft
Registered: Jul 2007
Posts: 369 |
Quoting Monte CarlosSo in cycle 55 DMA is still going on while in cycle 56 it's already over. That's why cpu can't access $d016 in cycle 55.
Perhaps one should try this with RamEx or SCPU?
No, DMA is going on until (including) cycle 54. But you can't write anything on the first available cycle, because that write is swallowed up during the three write-only cycles (normally 12-14).
All of this is described quite clearly in the vic article. |
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lft
Registered: Jul 2007
Posts: 369 |
Quoting Color BarMaybe you could postpone the badline condition until after the left border edge? Then you may be able to change $d016 in the left border and change it back again after it. Then force a badline condition.
Yes, that should work.
Quote:"Color Bar"]This will mess with the graphics on the badlines, I suppose. (If I understand it correctly, this is VSP, isn't it?).
It is VSP if the badline condition was triggered in idle mode. But you could also trigger it from display mode. For instance, you could use the "repeat row" trick to go from RC=7 to RC=0 without having a new badline. Then in the middle of that line, you can force a badline condition, which creates a partial FLI line (with the FLI bug somewhere in the middle of the line). |
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Oswald
Registered: Apr 2002
Posts: 5017 |
Quote: Quoting Oswaldbtw why the fuck do anyone call that DMA ? its a total misuse of the term
It's correct usage of the term. DMA can also be in the direction from memory to peripheral (as in the case with the VIC accessing main memory without CPU involvement). I don't know why the definition you quoted says otherwise.
its not correct usage, DMA is a technique to speed up I/O, esp. ment to ease up the CPU from the grunt work of copying bytes. The VICII is nor a peripheral, nor there's anything to speed up. Its wired into the system from day 0. There's no cpu job to speed up. There's no I/O. There's no peripheral.
DMA was invented after the c64 was released. How could it have DMA then ? But if you insist then we should call cpu mem accesses DMA too. Eventho it implies there's a no direct mem access too, which isnt there..
DMA stands for Direct Memory Access, a capability in modern computers that allows peripheral devices to send data to the motherboards memory without intervention from the CPU.
Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels |
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