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Krill
Registered: Apr 2002
Posts: 2856 |
Shortest code for stable raster timer setup
While working on my ICC 2019 4K entry (now postponed to ICC 2020, but i hope it'll be worth the wait), i came up with this (14 bytes):initstabilise lda $d012
ldx #10 ; 2
- dex ; (10 * 5) + 4
bpl - ; 54
nop ; 2
eor $d012 - $ff,x; 5 = 63
bne initstabilise; 7 = 70
[...]; timer setupThe idea is to loop until the same current raster line is read at the very beginning (first cycle) and at the very end (last cycle) of a raster line, implying 0 cycles jitter.
With 63 cycles per line on PAL, the delay between the reads must be 63 cycles (and not 62), reading $d012 at cycle 0 and cycle 63 of a video frame's last line (311), which is one cycle longer due to the vertical retrace.
The downside is that effectively only one line per video frame is attempted, so the loop may take a few frames to terminate, and the worst case is somewhere just beyond 1 second.
The upside is that it always comes out at the same X raster position AND raster line (0), plus it leaves with accu = 0 and X = $ff, which can be economically re-used for further init code.
Now, is there an even shorter approach, or at least a same-size solution without the possibly-long wait drawback? |
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Rastah Bar
Registered: Oct 2012
Posts: 336 |
How would one setup a timer in NTSC? Since 65 = 5*13 a timer period of 13 seems the most obvious choice. |
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Quiss
Registered: Nov 2016
Posts: 40 |
This is an idea I got after talking to Copyfault.
At least in the cycle-correct version of Vice (i.e., x64sc) this seems to work. Haven't tried on a real machine.
* = $0f00 ; Some address with (H+1)&1 = 0 and (H+1)&$10 = $10
ldy #$00
loop: ldx #$11
shx cont, y
cont: bpl loop
It uses the fact that we will AND the written value with H+1 unless a badline pauses the CPU between the third and fourth cycle of shx. The latter then changes the "bpl" into an "ora" and drops us out of the loop at horizontal position 61. |
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Rastah Bar
Registered: Oct 2012
Posts: 336 |
Only 9 bytes! Very nice use of the peculiarities of SHX too! |
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JackAsser
Registered: Jun 2002
Posts: 1995 |
Quote: This is an idea I got after talking to Copyfault.
At least in the cycle-correct version of Vice (i.e., x64sc) this seems to work. Haven't tried on a real machine.
* = $0f00 ; Some address with (H+1)&1 = 0 and (H+1)&$10 = $10
ldy #$00
loop: ldx #$11
shx cont, y
cont: bpl loop
It uses the fact that we will AND the written value with H+1 unless a badline pauses the CPU between the third and fourth cycle of shx. The latter then changes the "bpl" into an "ora" and drops us out of the loop at horizontal position 61.
Haha! Wow! |
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Burglar
Registered: Dec 2004
Posts: 1051 |
Quoting Quiss
* = $0f00 ; Some address with (H+1)&1 = 0 and (H+1)&$10 = $10
ldy #$00
loop: ldx #$11
shx cont, y
cont: bpl loop
wait what?? I need to look up SHX... at first glance this does not make any sense to me :) |
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ChristopherJam
Registered: Aug 2004
Posts: 1382 |
Holy shit, that’s brilliant! Well found. |
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Burglar
Registered: Dec 2004
Posts: 1051 |
even Crossbow cannot beat this! |
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chatGPZ
Registered: Dec 2001
Posts: 11154 |
i so have to steal this and use as an example in my pdf :)
edit: quick test on C64 confirms it works :) |
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JackAsser
Registered: Jun 2002
Posts: 1995 |
Quote: i so have to steal this and use as an example in my pdf :)
edit: quick test on C64 confirms it works :)
So at a controlled X pos but at a ”random” y*8+c pos depending on $d011, which is good enough to launch a 63c timer ofc. |
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TWW
Registered: Jul 2009
Posts: 541 |
Quote: This is an idea I got after talking to Copyfault.
At least in the cycle-correct version of Vice (i.e., x64sc) this seems to work. Haven't tried on a real machine.
* = $0f00 ; Some address with (H+1)&1 = 0 and (H+1)&$10 = $10
ldy #$00
loop: ldx #$11
shx cont, y
cont: bpl loop
It uses the fact that we will AND the written value with H+1 unless a badline pauses the CPU between the third and fourth cycle of shx. The latter then changes the "bpl" into an "ora" and drops us out of the loop at horizontal position 61.
Damn, nice one. |
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