| |
Oswald
Registered: Apr 2002
Posts: 5022 |
drivecoding
Hi people!
I have looked for info on the topic with google, but I think there is very little info on this out there. Anyone can post some useful links?
other questions:
- anyone can give me a sourcecode which would upload any kind of prg to the drive, and execute it ?
- why atn cant be used to send bits ?
- where is the entry point in the drive rom of the soft reset routine?
|
|
| |
cadaver
Registered: Feb 2002
Posts: 1153 |
Once in my life I was in similar position, therefore I wrote the fastloader rants at covertbitops :)
I recommend:
Marko Mäkelä's adaptation/rework of GI JOE loader, can be tricky with all conditional defines for C64/VIC20 etc.
http://www.ffd2.com/fridge/io/irqloader.s
My fastloader rants + the loadersystem
http://www.student.oulu.fi/~loorni/covert/rants/irqload.htm
http://www.student.oulu.fi/~loorni/covert/rants/2bitload.htm
http://www.student.oulu.fi/~loorni/covert/tools/loader.zip
Cybernator's loader (does everything hard way, no drive-rom routine support used)
http://www.geocities.com/lazeristoski/ctsload.zip
ATN can be used by the computer as a timing signal, but the drive must anticipate each ATN bit value and set another bit in its serial bus register ($1800), otherwise it pulls DATA low automatically because of a circuit designed to respond to the ATN. Because of DATA pulled low by all other drives on the bus, it will work with only one drive.
The reset vector can be reached by doing jmp ($fffa). But I've found it nicest to exit by jumping to the Initialize routine $d005, so that one can safely mess with all the drive-ram buffers one wants, including the BAM.. |
| |
Radar
Account closed
Registered: Jul 2003
Posts: 259 |
Quote: Hi people!
I have looked for info on the topic with google, but I think there is very little info on this out there. Anyone can post some useful links?
other questions:
- anyone can give me a sourcecode which would upload any kind of prg to the drive, and execute it ?
- why atn cant be used to send bits ?
- where is the entry point in the drive rom of the soft reset routine?
Look at all IFFL-routines back from 90-92. The scanner-code has been sent into the 1541-memory and got executed. That's the way we liked it ;-) Afterwards you can read bits/bytes out of the routine. Why not reading the 'Big 1541 Book' from Data Becker from 1988? There you will find all solutions to all your questions... |
| |
cadaver
Registered: Feb 2002
Posts: 1153 |
Ah, a mistake, reset vector is of course at $fffc. Btw I would be interested in sourcecode of IFFL routines too but all readily available sources, according to my searches, seem to be lame (ie. not real scanning IFFL, but instead read bytes off the file until correct position reached) |
| |
Radar
Account closed
Registered: Jul 2003
Posts: 259 |
Quote: Ah, a mistake, reset vector is of course at $fffc. Btw I would be interested in sourcecode of IFFL routines too but all readily available sources, according to my searches, seem to be lame (ie. not real scanning IFFL, but instead read bytes off the file until correct position reached)
Nah, that's just a trick just like reading seq-files and then calculating t/s/b. Look at the public ftp's and you'll find something neat then, eg. arnold-ftp
And btw, why did you start 3 threads with the same question? |
| |
Graham
Account closed
Registered: Dec 2002
Posts: 990 |
@oswald:
sending stuff to drive is fairly easy:
; send LISTEN to drive:
LDA $BA ; device number (usually 8)
JSR $FFB1 ; LISTEN
LDA #$6F ; secondary adress (15)
JSR $FF93 ; SECLSN
; send M-W command to drive:
LDA #"M"
JSR $FFA8 ; IECOUT
LDA #"-"
JSR $FFA8
LDA #"W"
JSR $FFA8
; send adress and size to drive:
LDA #$00 ; adress in drive (low byte)
JSR $FFA8
LDA #$04 ; adress in drive (high byte)
JSR $FFA8
LDA #$20 ; 32 bytes
JSR $FFA8
; transfer stuff:
LDY #$00
.bla
LDA drivestuff,Y
JSR $FFA8
INY
CPY #$20
BNE .bla
; send UNLISTEN to drive:
JSR $FFAE ; UNLSN
that's it. the maximum transfer size in one go is 36 bytes, so typically people will use the M-W command in 32 bytes chunks. |
| |
Oswald
Registered: Apr 2002
Posts: 5022 |
thanks for all the help so far!
atn seems to be quite tricky.
$1800:
Bit #4: ATNA OUT; 1 = Enable device presence detection by acknowledging ATN IN signals on DATA OUT
Bit #7: ATN IN; 0 = Low; 1 = High.
so this means, that bit 4 must be set high, to be able to read a high ATN signal on bit 7 ? but when c64 sets atn high this will also pull DATA to 0 ?
it looks that atn then can set to low by the c64 without bit 4 in 1800 being high, this is what I saw in krill's sources.
can anyone verify that this works the way I wrote?:)
|
| |
Graham
Account closed
Registered: Dec 2002
Posts: 990 |
if you want to read ATN IN you must set ATN OUT to 0, same with DATA and CLK. same with $DD00 in the c64, with the difference that the two IN bits are inverted there. |
| |
Oswald
Registered: Apr 2002
Posts: 5022 |
this is how krill did it:
(hope he wont mind, he released the source to public anyway)
LDA #$00
STA $1800 ;ATN 2 LO
BIT $1800
BPL *-3 ;wait 4 ATN LO
DSENDLUP LDX GCRSPLT3+1,Y
LDA NUGCRDEC-$09,X
LDX GCRSPLT2+1,Y
BIT $1800 ;wait 4 ATN HI
BMI *-3
STA $1800 ;send 2 bits
ASL A
ORA #%00010000
BIT $1800 ;wait 4 ATN LO
BPL *-3
STA $1800 ;send 2 bits,ATN to HI
LDA NUGCRDEC-$09,X
BIT $1800 ;wait 4 ATN HI
BMI *-3
STA $1800 ;send 2 bits ATN to LO
ASL A
ORA #%00010000
BIT $1800 ;wait 4 ATN LO
BPL *-3
why does he need to set atn out to high every second time?
maybe atn high can only be read when atn out is also high?
aint it possible to read atn lo/hi state leaving atn out 0 all the time? |
| |
Hoogo
Registered: Jun 2002
Posts: 102 |
If I remember it correctly, DATA works fine when ATN OUT of the floppy and of the C64 have the same value. It is part of the serial protocol that all devices on the bus shall pull Data down when ATN is set. In the 1541 that was partly done in hardware and partly in software. But I don't remember the exact meaning. |
| |
Oswald
Registered: Apr 2002
Posts: 5022 |
Quote: if you want to read ATN IN you must set ATN OUT to 0, same with DATA and CLK. same with $DD00 in the c64, with the difference that the two IN bits are inverted there.
it doesnt quite looks so in krill's source, he reads ATN IN without taking care of the state of DATA and CLK, but there is this fiddling with ATN OUT, even he cant explain why its there... |
| |
Cybernator
Registered: Jun 2002
Posts: 154 |
Quote: it doesnt quite looks so in krill's source, he reads ATN IN without taking care of the state of DATA and CLK, but there is this fiddling with ATN OUT, even he cant explain why its there...
You misunderstood Graham's point. When you want to read ATN IN, you must set ATN OUT to 0. When you want to read DATA IN, you must set DATA OUT to 0, etc... |
| |
Hoogo
Registered: Jun 2002
Posts: 102 |
Quote: it doesnt quite looks so in krill's source, he reads ATN IN without taking care of the state of DATA and CLK, but there is this fiddling with ATN OUT, even he cant explain why its there...
That ATN-Out in the floppy is not simply connected to the ATN-line like all the other in/outs... Damn, why can't I remember all the special things about it??
Krill's source looks like that to me: He wants to transfer bytes from Floppy to C64. The C64 alters ATN to ask for a new pair of bits. ATN-Out in the drive is set according to the state of the ATN-Line, so the DATA-Line works again and he can transfer without waiting for ATN 0. |
| |
cadaver
Registered: Feb 2002
Posts: 1153 |
Beware the wrath of NTSC power users if you go with using the ATN-line :) |
| |
raven
Account closed
Registered: Jan 2002
Posts: 137 |
Ok.. lets put some things in order.
Been awhile since i coded my loader but this is what i
remember:
First of all, this waits for ATN HI, not LO (as stated in
the source).
bit$1800
bpl *-3
Bit #7 is set to 1 when ATN signal on the bus is present.
Now, when a device gets the ATN signal from the 64 the hardware automatically responds to let the 64 know
it got the signal.
The response comes either in DATA or CLK (cant remember exactly which one).
In order to disable the auto-response, bit #4 of $1800
must be set to 1.
This is a must! right after the 64 sends an ATN HI signal,
you must set bit #4 to 1 or you'll get data corrupted.
Hope this helps :)
|
| |
anix
Account closed
Registered: Feb 2004
Posts: 35 |
maybe a bit off topic but i thought it might be appropriate...
anyone ever notice that digital world / samar makes the led on 1571 (others?) fade in and out while the demo runs? i thought it was neat :)
|
| |
Oswald
Registered: Apr 2002
Posts: 5022 |
raven: yep now krill's protocol is clear to me :)
anix: flashing the led is easy, it worx on 1541's too, altho you can just turn on/off the led with 1 bit, but if you -with changing periods of time- turn it on off fast, you can make it look brighter, darker. |
| |
anix
Account closed
Registered: Feb 2004
Posts: 35 |
oswald: i see, like pulse width modulation. |
| |
anix
Account closed
Registered: Feb 2004
Posts: 35 |
can anyone explain how the action/retro replay ramloader works? or perhaps a url to the AR sourcecodes to read... |
| |
Krill
Registered: Apr 2002
Posts: 2850 |
the ar loader fetches all sectors of a track and sends them over to the c64, into the ar's extra ram, undecoded (afair). only there, they are decoded and copied to the correct locations in the c64's mem. the most impressive thing with that loader is the transfer protocol, syncing by adding a cycle or not each 4 transferred bytes. but what exactly do you want to know with that loader? i once re-coded it btw to work without any extra memory, still with a track buffer on the c64 side. but there is a way to get around wasting $1500 bytes of memory. though, haven't applied it to that ar-like loader. i used such a technique in my newer irq loaders, check fixup#$00 for sources. fixup#$01 will be released when i find some more spare time for boring tasks like copypasting better routines to exisiting loaders ;) |
| |
Count Zero
Registered: Jan 2003
Posts: 1825 |
Krill explained it nicely.
The CRC decoding is indeed done on the c64 side. Still, the drivecode is pretty huge and even a single block file requires reading and transfer of a whole track ..
l8r
Count Zero/CyberpunX/SCS*TRC |
| |
Krill
Registered: Apr 2002
Posts: 2850 |
count zero: not with the approach i use. it scans a track for the needed sectors on the drive side, then fetches and transfers only those sectors.
it's ages ago since i had a look at that ar loader and my copy of it, still i think this technique can be applied to it. and it's not noticeably slower, since you need only one revolution to scan the sector links. and it's faster for the first and last track of a file, and faster for files with only a few blocks. the drive ram, however, might not be large enough for an updated ar loader, i still have to evaluate that. |
