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TIL: The instruction after SEI can be executed before a pending IRQ is handled
2017-11-07
15:56
Krill
Registered: Apr 2002
Posts: 2839
TIL: The instruction after SEI can be executed before a pending IRQ is handled
As described here:
http://visual6502.org/wiki/index.php?title=6502_Timing_of_Inter..
I never knew this, after all those years, and thought i'd share this as a heads-up.
Thanks to
Bubis
for pointing it out to me!
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2017-11-15
21:44
MagerValp
Registered: Dec 2001
Posts: 1055
Good points, and easy enough to test:
pendingirq2.prg
, same sequence of SYS calls as in comment #91. The instruction immediately following the sta $d01a, dey, is executed before the IRQ triggers (verified that VICE matches my C64). So this means that immediately writing the register in the VICE monitor with > d01a 01 doesn't match the behavior of sta $d01a, but I suppose that isn't too surprising.
It makes sense too - at least on the 65c02 IRQs are evaluated during the last cycle of the previous instruction, and what happens is that the next opcode is replaced by $00, forcing a BRK. NMOS 6502 presumably works the same.
2017-11-17
22:07
Copyfault
Registered: Dec 2001
Posts: 466
So my assumption was correct :)
Thanks to everyone for clarification, esp. to MagerValp for quickly mocking up a test prg.
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