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JackAsser
Registered: Jun 2002
Posts: 1990 |
NMI delay
How much is an NMI delayed if triggered during IRQ-setup? |
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Fungus
Registered: Sep 2002
Posts: 626 |
1 cycle I think?
Was talking to groepaz a couple months ago about "eaten IRQs" which is a bug in the 6502. I supposed if the NMI came at the wrong time after an IRQ the IRQ can be lost, or a BRK.
There was some talk about it on the 6502 site he linked. |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
what do you mean "during IRQ-setup"? |
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JackAsser
Registered: Jun 2002
Posts: 1990 |
Quote: 1 cycle I think?
Was talking to groepaz a couple months ago about "eaten IRQs" which is a bug in the 6502. I supposed if the NMI came at the wrong time after an IRQ the IRQ can be lost, or a BRK.
There was some talk about it on the 6502 site he linked.
In VICE it's definetly more than 1 cycle, but hard to tell. |
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JackAsser
Registered: Jun 2002
Posts: 1990 |
Quote: what do you mean "during IRQ-setup"?
When the CPU performs the 7-cycle IRQ-setup (i.e. push status etc on the stack). During that time NMIs won't interrupt and will be delayed. But it doesn't seem to be delayed the full 7 cycles (at least not in VICE, havn't tested on the real thing but this is surely emulated correctly anyways). |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
ok. for that case, basically look at it like your NMI interrupts a BRK instruction (because it IS a BRK instruction!).
and then to see the details, simulate in visual6502 :) i am still struggling at explaining this properly, it should be added to NMS :) |
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Oswald
Registered: Apr 2002
Posts: 5026 |
cool, this sounds like a yummy raster fx :) |
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Fungus
Registered: Sep 2002
Posts: 626 |
Oh you mean the lockout time before another NMI can occur, isn't it the instruction length, but... if NMI is held low then another one shouldn't be able to strike unless you are doing something weird. Are you using the CIA where the code is executed the so the flag is cleared automatically? That would present a problem. |
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JackAsser
Registered: Jun 2002
Posts: 1990 |
Quote: ok. for that case, basically look at it like your NMI interrupts a BRK instruction (because it IS a BRK instruction!).
and then to see the details, simulate in visual6502 :) i am still struggling at explaining this properly, it should be added to NMS :)
Struggling also (and already checked visual6502), hence I took the lazy path and just asked. :D |
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JackAsser
Registered: Jun 2002
Posts: 1990 |
Quote: Oh you mean the lockout time before another NMI can occur, isn't it the instruction length, but... if NMI is held low then another one shouldn't be able to strike unless you are doing something weird. Are you using the CIA where the code is executed the so the flag is cleared automatically? That would present a problem.
No no no not at all. Imagine u have a raster IRQ, and when the CPU performs the IRQ-load (i.e. push status, return address, read IRQ vector and jump (7c) ) an NMI occurs. This NMI will get delayed by that IRQ process, but how much at most? In VICE it looks like around 3-4 cycles, but I don't understand why. Why not 7c? |
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JackAsser
Registered: Jun 2002
Posts: 1990 |
Quote: cool, this sounds like a yummy raster fx :)
It depends on the max delay, hence my question. :D |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
start here:
https://web.archive.org/web/20141224041136/http://visual6502.or..
You'll be more confused than before :o) |
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JackAsser
Registered: Jun 2002
Posts: 1990 |
Quote: start here:
https://web.archive.org/web/20141224041136/http://visual6502.or..
You'll be more confused than before :o)
Haha, already did. Hence the question here. :D |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
also
https://web.archive.org/web/20210405071346/http://visual6502.or..
https://web.archive.org/web/20210405071501/http://visual6502.or.. |
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Fungus
Registered: Sep 2002
Posts: 626 |
Ah I see what you mean now, I'm not entirely sure either. |
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Krill
Registered: Apr 2002
Posts: 2854 |
Quoting JackAsserImagine u have a raster IRQ, and when the CPU performs the IRQ-load (i.e. push status, return address, read IRQ vector and jump (7c) ) an NMI occurs. This NMI will get delayed by that IRQ process, but how much at most? In VICE it looks like around 3-4 cycles, but I don't understand why. Why not 7c? Hazarding a guess, this seems rather analogous to the BA/AEC-goes-low VIC-takes-over-the-bus case (or REU DMA, for that matter).
Up to 3 write cycles (6502/6510 never needs more in a row, with any kind of interrupt being the worst case), then interruption, because it's safe only now.
Wouldn't be surprised if the NMI-on-top-of-IRQ and BA/AEC-low cases share some considerable assumptions, logic and circuitry. |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
To really get an answer to this the PLA ROM needs to be understood.
http://www.visual6502.org/JSSim/expert.html
https://www.pagetable.com/?p=410
https://www.pagetable.com/?p=39
"At the end of each instruction, the PLA causes the T bitfield to reset, so that the next instruction starts with T1=1 again."
"All interrupt and NMI requests are always delayed until the current instruction is finished, i.e. until T gets reset." |
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JackAsser
Registered: Jun 2002
Posts: 1990 |
Quote: To really get an answer to this the PLA ROM needs to be understood.
http://www.visual6502.org/JSSim/expert.html
https://www.pagetable.com/?p=410
https://www.pagetable.com/?p=39
"At the end of each instruction, the PLA causes the T bitfield to reset, so that the next instruction starts with T1=1 again."
"All interrupt and NMI requests are always delayed until the current instruction is finished, i.e. until T gets reset."
Given that and given that an IRQ really is a BRK-instruction under the hood we can assume the delay can be up to 7 cycles then? |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
If only it was that simple :o)
It might be a good idea to simulate and iterate too all possible timings (ie trigger the nmi in every possible half cycle of that "BRK") and then see what happens. If i understood the wiki correctly, there are still special cases to consider. |
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JackAsser
Registered: Jun 2002
Posts: 1990 |
Quote: If only it was that simple :o)
It might be a good idea to simulate and iterate too all possible timings (ie trigger the nmi in every possible half cycle of that "BRK") and then see what happens. If i understood the wiki correctly, there are still special cases to consider.
Yeah, someday. For now I simply made sure that my IRQs never collides with the NMIs. :) |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
BAH! DO IT! :D |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
Quote: Yeah, someday. For now I simply made sure that my IRQs never collides with the NMIs. :)
There's no real problem as both will trigger eventually. |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
The problem is having predictable timing in all cases. Of course they trigger (except when they don't - see the wiki pages). |
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JackAsser
Registered: Jun 2002
Posts: 1990 |
Quote: The problem is having predictable timing in all cases. Of course they trigger (except when they don't - see the wiki pages).
Exactly. My NMIs must NOT be delayed or this card house will fall completly and ungraceful. |
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Fungus
Registered: Sep 2002
Posts: 626 |
Quote: The problem is having predictable timing in all cases. Of course they trigger (except when they don't - see the wiki pages).
Yes this is what I was looking at too, to see in which instances the IRQ is "eaten". I need to do some simulations there too and see if this behavior can be documented so we know exactly when and how this can occur.
I was already aware of BRK can eat an IRQ and vice versa, but if NMI is also a BRK instruction then the same thing could happen. It's just a matter of under what circumstances... |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
Yes. Those wiki pages are very confusing for that matter, because they also consider cases that can never happen - in a C64 anyway. |
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Krill
Registered: Apr 2002
Posts: 2854 |
Quoting Martin PiperTo really get an answer to this the PLA ROM needs to be understood. Please don't call it PLA. It's not programmable, it's just a ROM. =) |
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JackAsser
Registered: Jun 2002
Posts: 1990 |
Quote: Quoting Martin PiperTo really get an answer to this the PLA ROM needs to be understood. Please don't call it PLA. It's not programmable, it's just a ROM. =)
The LA. :) |
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Krill
Registered: Apr 2002
Posts: 2854 |
Quoting JackAsserThe LA. :) Lookup array. Basically table. =) |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
Quote: Quoting Martin PiperTo really get an answer to this the PLA ROM needs to be understood. Please don't call it PLA. It's not programmable, it's just a ROM. =)
"it's actually a PLA"
https://retrocomputing.stackexchange.com/questions/15227/why-di.. |
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Krill
Registered: Apr 2002
Posts: 2854 |
Quoting Martin Piper"it's actually a PLA"
https://retrocomputing.stackexchange.com/questions/15227/why-di.. So, well, it's programmable (by whoever edits a mask and re-runs production), but not field programmable... essentially the same technology as ROM. Ooookay. :)
Easy counter: https://electronics.stackexchange.com/questions/5825/what-is-th.. =) |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
https://en.wikipedia.org/wiki/Programmable_logic_array
"the original 6502 chip contained a PLA"
It's obviously not a full ROM. |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
That's simply wrong. It's a decode ROM, no more, no less. (And yes, what Krill said. Its not a traditional ROM, sure. Its a logic array. And that kind of thing is usually called decode ROM - not PLA. PLA is programmable, not mask edited.) |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
Quote: That's simply wrong. It's a decode ROM, no more, no less. (And yes, what Krill said. Its not a traditional ROM, sure. Its a logic array. And that kind of thing is usually called decode ROM - not PLA. PLA is programmable, not mask edited.)
Wrong. The PLA in the 6502 is sparse. A full ROM maps every single output. The 6502 PLA saves space compared to a full ROM.
It's why we have illegal opcodes.
https://www.pagetable.com/?p=39 |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
You don't have to copypaste me the ill informed stuff that you found on reddit.
FPLA is a synonym for the (modern) FPGA btw - and has zero to do with the oldschool "PLA".
(yes, please inform me about how illegal opcodes work, i always wanted to know) |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
Quote: You don't have to copypaste me the ill informed stuff that you found on reddit.
FPLA is a synonym for the (modern) FPGA btw - and has zero to do with the oldschool "PLA".
(yes, please inform me about how illegal opcodes work, i always wanted to know)
Wrong again.
Look at the chip layout, it's obviously a PLA, not a full ROM.
http://www.visual6502.org/JSSim/expert.html?nosim=t&panx=110.5&.. |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
"approximately top fifth of the chip (with the regular rectangular pattern) is the **PLA** that decodes instructions."
https://www.righto.com/2013/01/a-small-part-of-6502-chip-explai..
Basically "paz" you're not considering the actual layout of the gates on the chip and instead applying your incorrect thinking from an incorrect understanding about some higher level context which isn't appropriate. |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
This explains why your PLA explanation is wrong "paz".
https://en.wikipedia.org/wiki/Programmable_logic_array
"In 1970, Texas Instruments developed a *mask-programmable IC*..." "...TI coined the term **Programmable Logic Array** for this device." |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
If you'd spend as much time programming as googling up your "knowledge", perhaps your verlet integration code would even be ready by now :) |
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Fungus
Registered: Sep 2002
Posts: 626 |
Martin, if you have nothing to add to this conversation, then kindly shut up. No one wants to argue with you about tangential subjects just so you can die on yet another hill about something you clearly misunderstand.
Good lord man... |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
Quote: If you'd spend as much time programming as googling up your "knowledge", perhaps your verlet integration code would even be ready by now :)
We can see when you're wrong when you go into irrelevant topics. |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
Quote: Martin, if you have nothing to add to this conversation, then kindly shut up. No one wants to argue with you about tangential subjects just so you can die on yet another hill about something you clearly misunderstand.
Good lord man...
It's directly relevant since it details exactly how the instructions work.
Paz is just wrong and trying to go into tangents instead of sticking to the topic. |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
It has been an irrelevant topic since post #28, so yes.
Everyone here knows already how illegal opcodes work and that incomplete decoding is involved. Really. If you want to call it PLA doesn't matter a single bit to the topic. |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
Quote: It has been an irrelevant topic since post #28, so yes.
Everyone here knows already how illegal opcodes work and that incomplete decoding is involved. Really. If you want to call it PLA doesn't matter a single bit to the topic.
It's not me calling it a PLA, it's all the technical sources demonstrating it's a PLA by the analysis of the gates on the chip. Meanwhile we have your lack of knowledge baseless claims.
The fact is "paz" you're just wrong on this topic as you are wrong on so many other topics.
It's relevant to the topic because it directly deals with how the instructions are decoded. It's why studying at things like visual 6502 are important. |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
Quote: Martin, if you have nothing to add to this conversation, then kindly shut up. No one wants to argue with you about tangential subjects just so you can die on yet another hill about something you clearly misunderstand.
Good lord man...
oh and "No one wants to argue with you" if that were true then "paz" wouldn't be trying to reply to my posts right? But here we he, "paz" is spewing rubbish again and again. If you have a problem with irrelevant posts then talk to "paz". |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
Incomplete logic is not what defines a PLA. Removing "don't care" gates and logic from digital circuits is basically done everywhere, always (And the guys at MOS were really good at this, no doubt).
If you really want to pull the ancient TI terminology - even that doesn't apply. This refers to a standard component that can be customized by the customer. This is not the case for the 6502 either. The "custom chip" on the later AR5 hardware would be one for which this is the correct term, for example (iirc they coined yet another, different, term for this particular IC, because marketing reasons. Forgot what it was).
But what do i know. You are the expert.
(And yes, as soon as someone has to resort to calling names, you can be sure you have to take him serious. for real) |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
Quote: Incomplete logic is not what defines a PLA. Removing "don't care" gates and logic from digital circuits is basically done everywhere, always (And the guys at MOS were really good at this, no doubt).
If you really want to pull the ancient TI terminology - even that doesn't apply. This refers to a standard component that can be customized by the customer. This is not the case for the 6502 either. The "custom chip" on the later AR5 hardware would be one for which this is the correct term, for example (iirc they coined yet another, different, term for this particular IC, because marketing reasons. Forgot what it was).
But what do i know. You are the expert.
(And yes, as soon as someone has to resort to calling names, you can be sure you have to take him serious. for real)
Again incorrect.
https://en.wikipedia.org/wiki/Programmable_logic_array
"A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. "
It does not have to be programmable or customisable by the customer either. A mask programmed part is still a PLA, just like the one in the 6502.
Your incorrect statements are not supported by anything. |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
You are so right Martin. Thanks. |
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ChristopherJam
Registered: Aug 2004
Posts: 1381 |
Martin, the very page you keep linking to opens by saying that "A programmable logic array (PLA) is a kind of programmable logic device," with the last three words linking to a page that states in the first paragraph that "the function of a PLD is undefined at the time of manufacture."
The incomplete address decoding is entirely tangential to post manufacture programmability. You're correct in saying that it's not a ROM, but you're wrong about saying it's programmable. |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
Quote: Martin, the very page you keep linking to opens by saying that "A programmable logic array (PLA) is a kind of programmable logic device," with the last three words linking to a page that states in the first paragraph that "the function of a PLD is undefined at the time of manufacture."
The incomplete address decoding is entirely tangential to post manufacture programmability. You're correct in saying that it's not a ROM, but you're wrong about saying it's programmable.
And can be mask programmable... "MOS Technology / Commodore Semiconductor Group began producing a **mask-programmed PLA**"
That's the important bit along with how the actual gates are on the chip. The gates for that part of the 6502 are very clearly documented in multiple sources as a PLA. "the original **6502 chip contained a PLA** to direct various operations of the processor" |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
"MOS 906114-01. This was a **mask programmable** NMOS clone of the 82S100."
"PLA pinout
The PLAs used in the C64 ... not connected internally **for mask programmable parts**."
https://skoe.de/docs/c64-dissected/pla/c64_pla_dissected_a4ds.p.. |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
"the PLA may also be **mask-programmable** or field programmable. For a mask-programmable PLA, the user must submit a PLA program table to the manufacturer to produce a custom made PLA that has the required internal paths between inputs and outputs."
https://www.globalspec.com/reference/4274/348308/section-6-4-pr..
This rather proves the point that a PLA can be mask or field programmed. |
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JackAsser
Registered: Jun 2002
Posts: 1990 |
Guys. Start a new thread about that and please stay on topic. |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
So specifically relevant to the timing of NMI in the instruction cycle. You can trace each cycle and see how the PLA decoding is affected. For example:
Click here: http://www.visual6502.org/JSSim/expert.html?nosim=t&panx=111.6&..
It will zoom into the top left portion of the 6502, the top left pad is NMI and just underneath and to the right is the PLA. The regular grid arrangement.
You can click the "Trace more" button a few times until "nmi" is displayed in the trace, or add "nmi" to the "Trace these too:" box.
Each click of the "forward" button will advance half a cycle.
Once the demo code is running, or your own edited code, you can open the javascript debugger and execute:
setLow('nmi');
This click "forward" a few frames, then use:
setHigh('nmi');
This will let you see how the NMI signal is intercepted and processed at the PLA level and precisely test this for every half cycle in any instruction you choose to do this for.
The debugger should show: Exec: BRK(T0) around the time it is reading fffa/fffb etc
You can also trigger IRQs with: setLow('irq'); setHigh('irq'); and test what happens with NMI timing when processing an IRQ. |
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Martin Piper
Registered: Nov 2007
Posts: 645 |
And this help doc: https://www.nesdev.org/wiki/Visual6502wiki/JssimUserHelp
Has a nice useful section: set up some input pin transitions (Reset, IRQ, NMI, RDY)
Has this example URL which configures a NMI transition and updates the memory to allow for easily reproduced test cases with NMI and instruction timings, single stepping will show the same deterministic results each time and avoid having to do manual setup.
http://visual6502.org/JSSim/expert.html?graphics=f&loglevel=2&s.. |
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chatGPZ
Registered: Dec 2001
Posts: 11141 |
Quote:the user must submit a PLA program table to the manufacturer to produce a custom made PLA
hear hear >_< |
