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JackAsser
Registered: Jun 2002
Posts: 1989 |
NMI delay
How much is an NMI delayed if triggered during IRQ-setup? |
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Martin Piper
Registered: Nov 2007
Posts: 634 |
Quote: Incomplete logic is not what defines a PLA. Removing "don't care" gates and logic from digital circuits is basically done everywhere, always (And the guys at MOS were really good at this, no doubt).
If you really want to pull the ancient TI terminology - even that doesn't apply. This refers to a standard component that can be customized by the customer. This is not the case for the 6502 either. The "custom chip" on the later AR5 hardware would be one for which this is the correct term, for example (iirc they coined yet another, different, term for this particular IC, because marketing reasons. Forgot what it was).
But what do i know. You are the expert.
(And yes, as soon as someone has to resort to calling names, you can be sure you have to take him serious. for real)
Again incorrect.
https://en.wikipedia.org/wiki/Programmable_logic_array
"A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. "
It does not have to be programmable or customisable by the customer either. A mask programmed part is still a PLA, just like the one in the 6502.
Your incorrect statements are not supported by anything. |
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chatGPZ
Registered: Dec 2001
Posts: 11116 |
You are so right Martin. Thanks. |
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ChristopherJam
Registered: Aug 2004
Posts: 1378 |
Martin, the very page you keep linking to opens by saying that "A programmable logic array (PLA) is a kind of programmable logic device," with the last three words linking to a page that states in the first paragraph that "the function of a PLD is undefined at the time of manufacture."
The incomplete address decoding is entirely tangential to post manufacture programmability. You're correct in saying that it's not a ROM, but you're wrong about saying it's programmable. |
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Martin Piper
Registered: Nov 2007
Posts: 634 |
Quote: Martin, the very page you keep linking to opens by saying that "A programmable logic array (PLA) is a kind of programmable logic device," with the last three words linking to a page that states in the first paragraph that "the function of a PLD is undefined at the time of manufacture."
The incomplete address decoding is entirely tangential to post manufacture programmability. You're correct in saying that it's not a ROM, but you're wrong about saying it's programmable.
And can be mask programmable... "MOS Technology / Commodore Semiconductor Group began producing a **mask-programmed PLA**"
That's the important bit along with how the actual gates are on the chip. The gates for that part of the 6502 are very clearly documented in multiple sources as a PLA. "the original **6502 chip contained a PLA** to direct various operations of the processor" |
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Martin Piper
Registered: Nov 2007
Posts: 634 |
"MOS 906114-01. This was a **mask programmable** NMOS clone of the 82S100."
"PLA pinout
The PLAs used in the C64 ... not connected internally **for mask programmable parts**."
https://skoe.de/docs/c64-dissected/pla/c64_pla_dissected_a4ds.p.. |
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Martin Piper
Registered: Nov 2007
Posts: 634 |
"the PLA may also be **mask-programmable** or field programmable. For a mask-programmable PLA, the user must submit a PLA program table to the manufacturer to produce a custom made PLA that has the required internal paths between inputs and outputs."
https://www.globalspec.com/reference/4274/348308/section-6-4-pr..
This rather proves the point that a PLA can be mask or field programmed. |
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JackAsser
Registered: Jun 2002
Posts: 1989 |
Guys. Start a new thread about that and please stay on topic. |
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Martin Piper
Registered: Nov 2007
Posts: 634 |
So specifically relevant to the timing of NMI in the instruction cycle. You can trace each cycle and see how the PLA decoding is affected. For example:
Click here: http://www.visual6502.org/JSSim/expert.html?nosim=t&panx=111.6&..
It will zoom into the top left portion of the 6502, the top left pad is NMI and just underneath and to the right is the PLA. The regular grid arrangement.
You can click the "Trace more" button a few times until "nmi" is displayed in the trace, or add "nmi" to the "Trace these too:" box.
Each click of the "forward" button will advance half a cycle.
Once the demo code is running, or your own edited code, you can open the javascript debugger and execute:
setLow('nmi');
This click "forward" a few frames, then use:
setHigh('nmi');
This will let you see how the NMI signal is intercepted and processed at the PLA level and precisely test this for every half cycle in any instruction you choose to do this for.
The debugger should show: Exec: BRK(T0) around the time it is reading fffa/fffb etc
You can also trigger IRQs with: setLow('irq'); setHigh('irq'); and test what happens with NMI timing when processing an IRQ. |
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Martin Piper
Registered: Nov 2007
Posts: 634 |
And this help doc: https://www.nesdev.org/wiki/Visual6502wiki/JssimUserHelp
Has a nice useful section: set up some input pin transitions (Reset, IRQ, NMI, RDY)
Has this example URL which configures a NMI transition and updates the memory to allow for easily reproduced test cases with NMI and instruction timings, single stepping will show the same deterministic results each time and avoid having to do manual setup.
http://visual6502.org/JSSim/expert.html?graphics=f&loglevel=2&s.. |
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chatGPZ
Registered: Dec 2001
Posts: 11116 |
Quote:the user must submit a PLA program table to the manufacturer to produce a custom made PLA
hear hear >_< |
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