| |
JackAsser
Registered: Jun 2002
Posts: 1995 |
NMI delay
How much is an NMI delayed if triggered during IRQ-setup? |
|
... 45 posts hidden. Click here to view all posts....
|
| |
Oswald
Registered: Apr 2002
Posts: 5032 |
cool, this sounds like a yummy raster fx :) |
| |
Fungus
Registered: Sep 2002
Posts: 631 |
Oh you mean the lockout time before another NMI can occur, isn't it the instruction length, but... if NMI is held low then another one shouldn't be able to strike unless you are doing something weird. Are you using the CIA where the code is executed the so the flag is cleared automatically? That would present a problem. |
| |
JackAsser
Registered: Jun 2002
Posts: 1995 |
Quote: ok. for that case, basically look at it like your NMI interrupts a BRK instruction (because it IS a BRK instruction!).
and then to see the details, simulate in visual6502 :) i am still struggling at explaining this properly, it should be added to NMS :)
Struggling also (and already checked visual6502), hence I took the lazy path and just asked. :D |
| |
JackAsser
Registered: Jun 2002
Posts: 1995 |
Quote: Oh you mean the lockout time before another NMI can occur, isn't it the instruction length, but... if NMI is held low then another one shouldn't be able to strike unless you are doing something weird. Are you using the CIA where the code is executed the so the flag is cleared automatically? That would present a problem.
No no no not at all. Imagine u have a raster IRQ, and when the CPU performs the IRQ-load (i.e. push status, return address, read IRQ vector and jump (7c) ) an NMI occurs. This NMI will get delayed by that IRQ process, but how much at most? In VICE it looks like around 3-4 cycles, but I don't understand why. Why not 7c? |
| |
JackAsser
Registered: Jun 2002
Posts: 1995 |
Quote: cool, this sounds like a yummy raster fx :)
It depends on the max delay, hence my question. :D |
| |
chatGPZ
Registered: Dec 2001
Posts: 11154 |
start here:
https://web.archive.org/web/20141224041136/http://visual6502.or..
You'll be more confused than before :o) |
| |
JackAsser
Registered: Jun 2002
Posts: 1995 |
Quote: start here:
https://web.archive.org/web/20141224041136/http://visual6502.or..
You'll be more confused than before :o)
Haha, already did. Hence the question here. :D |
| |
chatGPZ
Registered: Dec 2001
Posts: 11154 |
also
https://web.archive.org/web/20210405071346/http://visual6502.or..
https://web.archive.org/web/20210405071501/http://visual6502.or.. |
| |
Fungus
Registered: Sep 2002
Posts: 631 |
Ah I see what you mean now, I'm not entirely sure either. |
| |
Krill
Registered: Apr 2002
Posts: 2856 |
Quoting JackAsserImagine u have a raster IRQ, and when the CPU performs the IRQ-load (i.e. push status, return address, read IRQ vector and jump (7c) ) an NMI occurs. This NMI will get delayed by that IRQ process, but how much at most? In VICE it looks like around 3-4 cycles, but I don't understand why. Why not 7c? Hazarding a guess, this seems rather analogous to the BA/AEC-goes-low VIC-takes-over-the-bus case (or REU DMA, for that matter).
Up to 3 write cycles (6502/6510 never needs more in a row, with any kind of interrupt being the worst case), then interruption, because it's safe only now.
Wouldn't be surprised if the NMI-on-top-of-IRQ and BA/AEC-low cases share some considerable assumptions, logic and circuitry. |
| Previous - 1 | 2 | 3 | 4 | 5 | 6 - Next |
