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Monte Carlos
Registered: Jun 2004
Posts: 358 |
Left/Right Border switching in middle of rasterline
The last days i experimented a little with bit 3 of $d016. I had the brainfart to broaden the border on the left and keep it normal on the right. Disappointingly, this seems to work only in every non badline. If i try to switch bit 3 of $d016 during a badline i either get both left and right borders equal or i turn off the border completely for the next rasterline. Does somebody have an explanation in terms of internal VIC timing? I also tried modifying the timing with sprites or HSP to be able to write to $d016 in the correct cycle. |
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chatGPZ
Registered: Dec 2001
Posts: 11351 |
Quote: its not correct usage, DMA is a technique to speed up I/O, esp. ment to ease up the CPU from the grunt work of copying bytes. The VICII is nor a peripheral, nor there's anything to speed up. Its wired into the system from day 0. There's no cpu job to speed up. There's no I/O. There's no peripheral.
DMA was invented after the c64 was released. How could it have DMA then ? But if you insist then we should call cpu mem accesses DMA too. Eventho it implies there's a no direct mem access too, which isnt there..
DMA stands for Direct Memory Access, a capability in modern computers that allows peripheral devices to send data to the motherboards memory without intervention from the CPU.
Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels
WHAT THE ACTUAL FUCK.
whatever the source for this "knowledge" is - delete it from your memory. srsly. |
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lft
Registered: Jul 2007
Posts: 369 |
Quoting Monte CarlosAbout the VSP:
I tried to VSP in line $30 to delay all the internal vic timing for the whole screen.
There is no way to delay all the internal vic timing for the whole screen. VSP is for increasing the video matrix offset by 1..39. |
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Monte Carlos
Registered: Jun 2004
Posts: 358 |
Ok, maybe not for the whole screen but the badline starts as soon as the badline condition is fulfilled. So the appropriate write to $d011 should start the badline condition anywhere in the visible area and this also starts the internal VIC timing of the rasterline. Or did i understand something wrong, here? |
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Martin Piper
Registered: Nov 2007
Posts: 718 |
Writing to the VIC registers basically instructs it to directly read certain memory into its own internal state for later processing/display. Hence the VIC does DMA. |
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Monte Carlos
Registered: Jun 2004
Posts: 358 |
Maybe we should start a new topic about whats DMA and whats not if there is so much interest. |
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Peiselulli
Registered: Oct 2006
Posts: 81 |
Write demos for the Atari 2600. THAT is a computer without DMA ... |
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Oswald
Registered: Apr 2002
Posts: 5086 |
Quote: Writing to the VIC registers basically instructs it to directly read certain memory into its own internal state for later processing/display. Hence the VIC does DMA.
VICII reads the memory wether the cpu touches any of its registers or not. its a wired behaviour. if you skew your perspective enough tho I admit it can be viewed as DMA, but thats not my view.
DMA usually refers to speed up copying between memory and a true I/O device, or memcopy, etc. usually involves a DMA controller too. |
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JackAsser
Registered: Jun 2002
Posts: 2014 |
Quote: VICII reads the memory wether the cpu touches any of its registers or not. its a wired behaviour. if you skew your perspective enough tho I admit it can be viewed as DMA, but thats not my view.
DMA usually refers to speed up copying between memory and a true I/O device, or memcopy, etc. usually involves a DMA controller too.
So writing to $d011 doesn't affect that "hardwired" behaviour at all? :) |
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Oswald
Registered: Apr 2002
Posts: 5086 |
Quote: So writing to $d011 doesn't affect that "hardwired" behaviour at all? :)
almost any register change affects it :) but yeah the way it stops the cpu to access mem via bus lines resembles certain modern DMA behaviour. |
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lft
Registered: Jul 2007
Posts: 369 |
Quoting Monte CarlosOk, maybe not for the whole screen but the badline starts as soon as the badline condition is fulfilled. So the appropriate write to $d011 should start the badline condition anywhere in the visible area and this also starts the internal VIC timing of the rasterline. Or did i understand something wrong, here?
True, but you only change where the badline starts. It always ends at a fixed position (leaving you at cycle 55). |
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