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Monte Carlos
Registered: Jun 2004
Posts: 358 |
Left/Right Border switching in middle of rasterline
The last days i experimented a little with bit 3 of $d016. I had the brainfart to broaden the border on the left and keep it normal on the right. Disappointingly, this seems to work only in every non badline. If i try to switch bit 3 of $d016 during a badline i either get both left and right borders equal or i turn off the border completely for the next rasterline. Does somebody have an explanation in terms of internal VIC timing? I also tried modifying the timing with sprites or HSP to be able to write to $d016 in the correct cycle. |
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lft
Registered: Jul 2007
Posts: 369 |
You'd have to reset to narrow border in cycle 55. (It needs to be wide during the badline DMA, then become narrow before the first half of cycle 56.) But you can't do that, since the write access will happen on cycle 12 instead. |
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Monte Carlos
Registered: Jun 2004
Posts: 358 |
Ok, but what is the difference than to the other way round, when one opens the border?
Isn't it the same cycle the write has to be performed? |
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lft
Registered: Jul 2007
Posts: 369 |
Nope, then you want the vic to "miss" both occasions where the border might be turned on. So you reconfigure it during cycle 56. In your scenario, you want it to "hit" the first occasion. |
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Monte Carlos
Registered: Jun 2004
Posts: 358 |
So in cycle 55 DMA is still going on while in cycle 56 it's already over. That's why cpu can't access $d016 in cycle 55.
Perhaps one should try this with RamEx or SCPU? |
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chatGPZ
Registered: Dec 2001
Posts: 11351 |
that doesnt enable you to write to registers when a DMA is going on either :) |
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Monte Carlos
Registered: Jun 2004
Posts: 358 |
No, i meant using reu and dma transfer to $d016 |
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Oswald
Registered: Apr 2002
Posts: 5086 |
VICII will either read those 40 bytes on a badline or display garbage. guess which will happen with REU attached ?
btw why the fuck do anyone call that DMA ? its a total misuse of the term:
Direct Memory Access (DMA) is a capability provided by some computer bus architectures that allows data to be sent directly from an attached device (such as a disk drive) to the memory on the computer's motherboard. The microprocessor is freed from involvement with the data transfer, thus speeding up overall computer operation. |
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Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
Maybe you could postpone the badline condition until after the left border edge? Then you may be able to change $d016 in the left border and change it back again after it. Then force a badline condition. This will mess with the graphics on the badlines, I suppose. (If I understand it correctly, this is VSP, isn't it?). |
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lft
Registered: Jul 2007
Posts: 369 |
Quoting Oswaldbtw why the fuck do anyone call that DMA ? its a total misuse of the term
It's correct usage of the term. DMA can also be in the direction from memory to peripheral (as in the case with the VIC accessing main memory without CPU involvement). I don't know why the definition you quoted says otherwise. |
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lft
Registered: Jul 2007
Posts: 369 |
Quoting Monte CarlosSo in cycle 55 DMA is still going on while in cycle 56 it's already over. That's why cpu can't access $d016 in cycle 55.
Perhaps one should try this with RamEx or SCPU?
No, DMA is going on until (including) cycle 54. But you can't write anything on the first available cycle, because that write is swallowed up during the three write-only cycles (normally 12-14).
All of this is described quite clearly in the vic article. |
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