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2020-01-14 13:33

Krill

Registered: Apr 2002
Posts: 2847

C-64 coding cargo cults

The most-discussed coding cargo cult on the C-64 is probably SEI/CLI around interrupt setup code.

Here's another one: acknowledging VIC raster interrupts.

According to the datasheet http://archive.6502.org/datasheets/mos_6567_vic_ii_preliminary... an active VIC interrupt is acknowledged by writing a "1" to the corresponding bit in $d019.

The usual way to achieve this seems to be "DEC $D019" and to a lesser extent other read-modify-write instructions, saving a few bytes and/or cycles compared to "LDA $D019 : STA $D019" or "LDA #$xF : STA $D019".
This works because RMW instructions on 6502/6510 read a value (here, the pending interrupts) and write the same value again (clearing the interrupt latches) before writing the modified value.
This is also why this technique does not work on SuperCPU's 65816 in native mode, as its RMW instructions lack the dummy-write of the unmodified value.

Now, the cargo cult bit is this: For raster interrupts, it suffices to write any value with bit 0 set (likewise for other VIC interrupts). Clearing all VIC interrupts can be achieved by writing any value with bits 0..3 set.

So, you can save 2 cycles by simply recycling any register value that happens to have bit 0 set, writing that one to $d019 to acknowledge a VIC raster interrupt.

Please post other coding cargo cults here. =)

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2020-02-08 22:22

Raz
Account closed

Registered: Aug 2003
Posts: 16

Really nice discussion thread here. I have to admit, I was not aware of the just set bit 0 for ACK of IRQs. I have always done ALS $d019 out of habit.

Reading through the comments, one thing I have realized, is that I have changed my coding style somewhat, after my long break from c64 coding (and coding a lot of scientific software in "real life"): Now I think a lot about readability vs. size/speed in non time critical parts of the code. I don't shy away from doing:

LDA vic_register
AND mask
ORA things_to_set
STA vic_register

If it's just some setup code, but I certainly just do LDA/STA if it matters (and I've, btw, started to do much more timer-critical code, which was otherwise never my strong side back in the day).

Cheers
-Raz

2020-02-10 06:24

ChristopherJam

Registered: Aug 2004
Posts: 1378

Here's another one.

"You can avoid the ADSR bug by using a specific register write order, independent of instrument design"

Um, just no. You can certainly avoid breaking many well behaved instruments by not deviating from the write order they were designed for, but if you're porting instruments from a routine that used a different ordering there's a fair chance you will break them by switching to your favourite.

The advice given just seems to work because
a) many routines already use the same order.
and
b) writing register 04 after register 05 at start of note avoids changing attack just after setting the gate bit, which can be an issue if the preceding note had a long attack and you don't want to stall a fast one. (A functional HR can also avoid this issue)

The important thing is not using a register write to switch from a slow (high register value) rate to a fast one, unless you desire or can tolerate a 33ms freeze.

It makes no difference whether the rate change comes from switching the value for the current envelope phase (eg changing attack after setting gate), or from toggling the gate bit (eg setting gate to change from decay rate to attack rate).

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