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Forums > C64 Coding > VIA 6522 latching still unemulated.
2021-04-08 13:12
Zibri
Account closed

Registered: May 2020
Posts: 304		 VIA 6522 latching still unemulated.

let's imagine that on disk are recorded 5 bytes:
we call them x1 x2 x3 x4 and x5

now imagine we positioned in front of them, we skip 3 and read the fourth.
if to do that you use this code:

    CLV
    LDA $1C01   ; A here contains X1
    LDY #$03
loop:
    BVC loop
    CLV
    DEY
    BNE loop
    LDA $1C01 ;  A = X1 on RH and X5 on emulators


on vice, pi1541 and ultimate64/u2+
A will contain "x5".
But on real hardware it will contain X1.

The following code instead will work on both:
        CLV
        LDA $1C01   ; A here contains X1
        LDY #$03
loop:
        BVC loop
        CLV
        DEY
        BNE loop
        LDA $1C0F ; A = X5


That happens because 1C01 keeps the last byte READ (with any LOAD operation or any other cpu instruction that does a READ) while 1C0F contains the actual shift register.

Note:
also putting a "useless" LDA $1C01 inside the loop and the reading 1C01 will work too. But still I think that's an important feature present on BOTH VIA CHIPS that should be emulated.
 
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2021-07-19 22:25
willymanilly

Registered: Jan 2016
Posts: 27		 Quote: It seems that $6f in $1c0c causes loading to break on (some) real hardware, as well. In particular, I just received word that an 1541 with an older Alps drive mechanism (and a short board) won't run Freespin either, but works fine if $1c0c is set $ee.

I'm light of Freespin failing on some real hardware I'm thinking now the issue is more likely to do with the length of the byte ready signal which triggers the port latching.

$ee in 1c0c should always guarantee valid data will be on the port pins because it triggers as soon as the byte ready signal asserts itself. If $6f is used the latching may occur when the shifter has already shifted another bit depending on when the byte ready signal resets itself.

Another useful test would be to determine how long the byte ready signal is for different drive models. I've already tested in emulation that shortening the length of the byte ready signal allows Freespin to run the complete demo without requiring a hack to the VIA port latching!
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