LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY EF64TestBench IS
END EF64TestBench;
 
ARCHITECTURE behavior OF EF64TestBench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ef3
    PORT(
         addr : INOUT  std_logic_vector(15 downto 0);
         data : INOUT  std_logic_vector(7 downto 0);
         n_dma : OUT  std_logic;
         ba : IN  std_logic;
         n_roml : IN  std_logic;
         n_romh : IN  std_logic;
         n_io1 : IN  std_logic;
         n_io2 : IN  std_logic;
         n_wr : IN  std_logic;
         n_irq : INOUT  std_logic;
         n_nmi : INOUT  std_logic;
         n_reset_io : INOUT  std_logic;
         clk : IN  std_logic;
         phi2 : IN  std_logic;
         n_exrom : INOUT  std_logic;
         n_game : INOUT  std_logic;
         button_a : IN  std_logic;
         button_b : IN  std_logic;
         button_c : IN  std_logic;
         n_led : OUT  std_logic;
         mem_addr : OUT  std_logic_vector(22 downto 0);
         mem_data : INOUT  std_logic_vector(7 downto 0);
         n_mem_wr : OUT  std_logic;
         n_mem_oe : OUT  std_logic;
         n_flash_cs : OUT  std_logic;
         n_ram_cs : OUT  std_logic;
         n_usb_txe : IN  std_logic;
         n_usb_rxf : IN  std_logic;
         usb_wr : OUT  std_logic;
         n_usb_rd : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal ba : std_logic := '0';
   signal n_roml : std_logic := '0';
   signal n_romh : std_logic := '0';
   signal n_io1 : std_logic := '0';
   signal n_io2 : std_logic := '0';
   signal n_wr : std_logic := '0';
   signal clk : std_logic := '0';
   signal phi2 : std_logic := '0';
   signal button_a : std_logic := '0';
   signal button_b : std_logic := '0';
   signal button_c : std_logic := '0';
   signal n_usb_txe : std_logic := '0';
   signal n_usb_rxf : std_logic := '0';

	--BiDirs
   signal addr : std_logic_vector(15 downto 0);
   signal data : std_logic_vector(7 downto 0);
   signal n_irq : std_logic;
   signal n_nmi : std_logic;
   signal n_reset_io : std_logic;
   signal n_exrom : std_logic;
   signal n_game : std_logic;
   signal mem_data : std_logic_vector(7 downto 0);

 	--Outputs
   signal n_dma : std_logic;
   signal n_led : std_logic;
   signal mem_addr : std_logic_vector(22 downto 0);
   signal n_mem_wr : std_logic;
   signal n_mem_oe : std_logic;
   signal n_flash_cs : std_logic;
   signal n_ram_cs : std_logic;
   signal usb_wr : std_logic;
   signal n_usb_rd : std_logic;

   signal c128_reset_mirror : std_logic;

   -- Clock period definitions
   constant clk_period : time := 40 ns; -- ef3 has a 25mhz clock
   constant C128_clk_period : time := 500ns; -- 1mhz mode
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: ef3 PORT MAP (
          addr => addr,
          data => data,
          n_dma => n_dma,
          ba => ba,
          n_roml => n_roml,
          n_romh => n_romh,
          n_io1 => n_io1,
          n_io2 => n_io2,
          n_wr => n_wr,
          n_irq => n_irq,
          n_nmi => n_nmi,
          n_reset_io => n_reset_io,
          clk => clk,
          phi2 => phi2,
          n_exrom => n_exrom,
          n_game => n_game,
          button_a => button_a,
          button_b => button_b,
          button_c => button_c,
          n_led => n_led,
          mem_addr => mem_addr,
          mem_data => mem_data,
          n_mem_wr => n_mem_wr,
          n_mem_oe => n_mem_oe,
          n_flash_cs => n_flash_cs,
          n_ram_cs => n_ram_cs,
          n_usb_txe => n_usb_txe,
          n_usb_rxf => n_usb_rxf,
          usb_wr => usb_wr,
          n_usb_rd => n_usb_rd
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 
	phi_process :process
	begin
		phi2 <= '0';
		wait for C128_clk_period;
		phi2 <= '1';
		wait for C128_clk_period;
	end process;

   -- Stimulus process
   stim_proc: process
   begin
		ba <= 'H';
		n_roml <= 'H';
		n_romh <= 'H';
		n_io1 <= 'H';
		n_io2 <= 'H';
		n_irq <= 'H';
		n_nmi <= 'H';
		n_game <= 'H';
		n_exrom <= 'H';
		n_DMA <= 'H';
		button_a <= '1';
		button_b <= '1';
		button_c <= '1';
		n_usb_txe <= '1';
		n_usb_rxf <= '1';
		addr <= b"1111111111111100";
		data <= b"10101010";
			
      n_reset_io <= '0'; -- 128 holds down reset
		c128_reset_mirror <= '0';
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for C128_clk_period*10;

		n_reset_io <= 'H'; -- 128 releases reset
		c128_reset_mirror <= 'H';
		
      -- insert stimulus here

      wait;
   end process;

END;

GND ------- switch --------+--- 4K7 R -- 3v3
    \ 100n C - + - 100K R -|
               |
               +------ inverter -------- CPLD

reset_boot_or_no_boot: process(n_sys_reset, reset_to_menu, clk)
 begin
        if n_sys_reset = '0' or reset_to_menu = '1' then
            easyflash_boot <= '1';
        elsif rising_edge(clk) then
            start_reset_i <= '0';
            if enable = '1' then
                if button_special_fn = '1' then
                    easyflash_boot <= '0';
                    start_reset_i <= '1';
                elsif button_crt_reset = '1' then
                    easyflash_boot <= '1';
                    start_reset_i <= '1';
                end if;
            end if;
        end if;
    end process;

    start_reset <= start_reset_i;

    ---------------------------------------------------------------------------
    -- The buttons will be enabled after all buttons have been released one
    -- time. This is done to prevent detection of button presses while the
    -- circuit is powered up.
    ---------------------------------------------------------------------------
    enable_buttons: process(clk)
    begin
        -- todo: Reset?
        if rising_edge(clk) then
            if button_a = '0' and button_b = '0' and
               button_c = '0' then
                buttons_enabled <= '1';
            end if;
        end if;
    end process enable_buttons;

signal a : std_logic := 'H';
signal b : boolean;
...
b <= (a = '1');
...

a ?= '1'