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LDX#40
Registered: Jun 2008
Posts: 8 |
Code Crashing On Some Hardware
I've come across a weird phenomenon with my two last productions - my code for initializing the raster interrupt causes crashes or rather ill raster behaviour on SOME real hardware. I would like to understand why this is happening. The two productions are:
The Brotherhood of Sleep 5.25"
Off the Grid
Here is the code causing the problem:
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sei
lda #<_NMI_UNACK ;change nmi vector to unacknowledge "routine"
sta $0318
lda #>_NMI_UNACK
sta $0319
lda #$00
sta $dd0e ;stop timer a
sta $dd04 ;set timer a to 0, after starting nmi will occur immediately
sta $dd05
lda #$81
sta $dd0d ;set timer a as source for nmi
lda #$01
sta $dd0e ;start timer a and trigger nmi
lda #$7f ;turn off interfering CIA interrupts
sta $dc0d
lda #$01 ;enable raster interrupts (and only those)
sta $d01a
lda #$fb ;set raster trigger
sta $d012
lda $d011 ;including clearing bit 8 of raster register
and #$7f
sta $d011
lda #<_IRINTRO ;set address of initial interrupt routine
sta $fffe
lda #>_IRINTRO
sta $ffff
lda #$35 ;switch off basic rom & kernal (bit 0 = 0)
sta $01
cli
lsr $dc0d ;acknowledge any pending interrupts
lsr $d019
jmp *
;==================
;leave nmi unacknowledged
_NMI_UNACK rti ;nmi left unacknowledged
;==================
_IRINTRO lsr $d019 ;acknowledge interrupt
inc $d020
inc $0400
lda #$fb ;set raster trigger
sta $d012
rti
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The solution was to place the LSR $DC0D and LSR $D019 right after the SEI (somebody suggested putting them even before the SEI). Also, LSR $DC0D should be LDA $DC0D, because reading is sufficient to acknowledge the CIA interrupts.
With "Off the Grid" I also noticed that the timing of music an and graphics is a few frames off (graphics display later than they are supposed to).
Does anybody have any idea why this would work in emulation and on most machines I tried, but cause the problems on some machines?
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64core @ http://www.kunstscheisse.net/ldx40 |
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chatGPZ
Registered: Dec 2001
Posts: 11114 |
So find out whats different between the two. It might be something subtle as "different powerup values in the CIA timer" (your original code does not force load, so the first nmi happens at basically a random offset) |
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LDX#40
Registered: Jun 2008
Posts: 8 |
Interesting idea. Thanks for the input.
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64core @ http://www.kunstscheisse.net/ldx40 |
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Raistlin
Registered: Mar 2007
Posts: 557 |
Yep, I agree with Groepaz. Not all hardware is the same - but you might only see differences when dealing with things that are generally unpredictable. |
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ThunderBlade
Registered: Jan 2002
Posts: 75 |
Maybe one machine has a 6526, the other a 6526A - a new difference between those two then? |
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chatGPZ
Registered: Dec 2001
Posts: 11114 |
there is zero difference between those, they are infact the very same chip, just tested/rated for different speed. You probably mean 6526 vs 8521 - i doubt that is the problem though. Its just glitchy code :) |
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tlr
Registered: Sep 2003
Posts: 1714 |
Quote: there is zero difference between those, they are infact the very same chip, just tested/rated for different speed. You probably mean 6526 vs 8521 - i doubt that is the problem though. Its just glitchy code :)
Well, from what I gather: What used to be called 6526A (as it was commonly printed on them) is now often called 8521.
The difference in practice is that timer interrupts fires a cycle faster on the latter (or was it the other way around?). |
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chatGPZ
Registered: Dec 2001
Posts: 11114 |
8521 were sold packaged as 6526 - yes :) and not limited to 6526A, also regular ones.
In any case, that shouldnt be the problem here. |
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ThunderBlade
Registered: Jan 2002
Posts: 75 |
Quote: 8521 were sold packaged as 6526 - yes :) and not limited to 6526A, also regular ones.
In any case, that shouldnt be the problem here.
The difference in practice is that timer interrupts fires a cycle faster on the latter -> Yes, that's the *known* difference. My question was if in the case discussed here, the working vs. not working setup maybe a different type of CIA. The LSR vs. LDA clearly isn't right, so different variants of the CIA might react differently. |
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Copyfault
Registered: Dec 2001
Posts: 466 |
Reading post#4 by Groepaz, I tend to translate ThunderBlades replies into the question wether there are specific power up values coupled to the CIA type.
This is an interesting question indeed and should be examined closer. Guess we need another collective effort to find out (and some test prog for this, to start with...) |
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tlr
Registered: Sep 2003
Posts: 1714 |
There is also the issue of the MCBASE initial value. On 6569's it tends to be $3f, making the first display of a sprite after power up wrap a few times.
This can mess up timing in the initialization in some rare cases if not cared for by "flushing" the sprites before using them. |
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