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Forums > C64 Coding > Some sort of multithreading.

2008-04-08 22:51

gregg
Account closed

Registered: Apr 2005
Posts: 56

Some sort of multithreading.

About a week ago the topic multithreading came up on #c-64. So today I gave it a try. However, there's something wrong with my code and I can't really figure out what it is.

A short description: I have a fixed number of threads running and a CIA IRQ deals with context switching in a round-robin fashion. Every IRQ I save all current state data (SP, status register, PC, A, X, Y) in a structure and fetch the state data for the next thread.

In this example the first thread increments the screen background color (fast), while the second thread changes the border background color (slow). However the wait in the second thread runs too fast every other time, and I have no idea why. It's probably something wrong with the context switch stuff, maybe some of you could take a look at it?

Sources are for ACME.

!to "threading.prg",cbm
!cpu 6510
;!source "mylib.a"
!macro basic_header .a, .b, .c, .d {
        *= $0801
        !byte <.eol,>.eol,0,0,$9e
        !text .a, .b, .c, .d
.eol:   !byte 0,0,0
}

num_threads = 2
thread_num = $fd		; current thread number

;--------------------------------------------------------------------------
+basic_header "2", "0", "6", "1"

*= $080d

init:	sei
		; set up context switch IRQ
		lda #$35
		sta $01

		lda #<context_switch
		ldx #>context_switch
		sta $fffe
		stx $ffff
		
		lda #0
		sta thread_num

		cli
		jmp thread1

;--------------------------------------------------------------------------
context_switch:
		pha
		txa
		pha
		tya
		pha
		lda $dc0d

		; save current thread
		lda thread_num
		; *8
		asl
		asl
		asl
		tay
		; save A,X,Y
		pla
		sta thread_data+6,y
		pla
		sta thread_data+5,y
		pla
		sta thread_data+4,y
		; save PSW
		pla
		sta thread_data+1,y
		; save PC
		pla
		sta thread_data+2,y
		pla
		sta thread_data+3,y
		; save SP
		tsx
		txa
		sta thread_data,y

		; next thread, wraparound
		ldy thread_num
		iny
		cpy #num_threads
		bne +
		ldy #0
+		sty thread_num

		; *8
		tya
		asl
		asl
		asl
		tay

		; restore thread data
		; stack pointer first
		lda thread_data,y
		tax
		txs
		; push PC, PSW for RTI
		lda thread_data+3,y
		pha
		lda thread_data+2,y
		pha
		lda thread_data+1,y
		pha
		; push registers
		lda thread_data+6,y
		pha
		lda thread_data+5,y
		pha
		lda thread_data+4,y
		pha

		pla
		tay
		pla
		tax
		pla
		rti
	
;--------------------------------------------------------------------------
thread1:
		inc $d021
		ldy #$02
		jsr wait2
		jmp thread1


thread2:
		inc $d020
		ldy #$80
		jsr wait2
		jmp thread2
		
wait2:
-		ldx #0
		dex
		bne *-1
		dey
		bne -
		rts

;--------------------------------------------------------------------------
thread_data:
	!fill 8, 0
	!byte $ff-$40, $22, <thread2, >thread2, 0,0,0,0

... 211 posts hidden. Click here to view all posts....

2008-04-15 19:37

Skate

Registered: Jul 2003
Posts: 492

@Oswald: Hmmm, it seems like you have peeked at wikipedia for Hyper-Threading too ;)

Actually my comment was supporting yours more than others but you completely turned your shields on.

Btw, I'm actively using multi-threading in my professional life. I'm not talking theoretically. If something I said doesn't exactly match with a "wikipedia" definition, I don't give a shit.

2008-04-16 04:50

The Shadow

Registered: Oct 2007
Posts: 304

During this argument between modern supercoders, I have an irq of my own. Can someone please explain how a double irq works? Is it an interrupt within an interrupt or what?

2008-04-16 05:58

Stryyker

Registered: Dec 2001
Posts: 465

Quote: During this argument between modern supercoders, I have an irq of my own. Can someone please explain how a double irq works? Is it an interrupt within an interrupt or what?

http://codebase64.org/doku.php?id=base:double_irq has some code. It is to make cycle exactle interrupts typically for raster effects/timing like VIC tricks.

2008-04-16 10:28

Martin Piper

Registered: Nov 2007
Posts: 647

Quote: you are right, you have wrote about operating levels, searching for that doesnt gives any clear definition, so lets play with your definition from now on:

"6502 does have two operating levels, in the context of this subject. IRQ mode and the mainline mode"

reading the status of the I flag doesnt helps. Since you can issue a SEI/CLI regardless you're in "irq" or "mainline" "mode", there's no way to tell the difference. you can never tell if the I flag was set by code or HW.

"Since the instruction execution changes if the interrupt disable bit is clear and the IRQ line goes low, then you're wrong."

that can be parodized nicely: since the instruction execution changes if the C/V/Z/M/B flag bit is clear then you're wrong. for example the code that has been jumped on by a BCC instuction is in 'c' bit set operating level. ;)

as there is no C/V/Z/M/B bit set/clear operating level on the 6510, so there is no I bit set/clear operating level.

You are wrong because reading the interrupt disable flag does allow the code to detect what operating level it is running in. This refutes your earlier statement "I can sei/cli in both "modes" and there's no way to determine if the cpu is running in irq or main program."
Obviously because the code can determine what operating level it is running in.

Being able to change between the two operating levels by using SEU/CLI is irrelevant to the point I am making. It is also irrelevant, to the point that I am making, that it is not possible to detect if the interrupt disable flag is set by software or hardware.

Since it is shown how you are wrong in the first part of your post now we get onto why you are wrong in the second half.

If you again read post 95 then it is clear that the intruction execution changes are related to the opcode fetch and the state of the IRQ line combined with the interrupt disable flag. Therefore your point about the C/V/Z/M/B and the branches is a red herring logical fallacy. You are also wrong because you are not accounting for the definition of operating level as defined in the scope of this topic.

2008-04-16 10:35

Martin Piper

Registered: Nov 2007
Posts: 647

Quote: SEI does not change operating level. It only blocks IRQs. Interrupts can still happen - NMI. It is still an interrupt and can be used for task scheduling.

"Operating level" in the context of this topic is defined in post 80 as "One level is when it is executing an IRQ. The other not running an IRQ, we will call this the mainline."

Then if you read post 85 I specifically mention "Note we are not mentioning the NMI here but that also interrupts the IRQ and mainline mode."

So by saying "It [SEI] only blocks IRQs" means that SEI does change the operating level as defined in the scope of this topic.

2008-04-16 10:50

Oswald

Registered: Apr 2002
Posts: 5031

here's your definition wisey:

"In the context of this discussion the 6502 has two operating levels. One level is when it is executing an IRQ. The other not running an IRQ, we will call this the mainline."

as you cannot decide based on the I bit or whatever, wether cpu is executing an irq or not, you dont have two operating whatevers, as when two whatever cannot be told appart its the same whatever.

2008-04-16 10:54

Oswald

Registered: Apr 2002
Posts: 5031

Quote: @Oswald: Hmmm, it seems like you have peeked at wikipedia for Hyper-Threading too ;)

Actually my comment was supporting yours more than others but you completely turned your shields on.

Btw, I'm actively using multi-threading in my professional life. I'm not talking theoretically. If something I said doesn't exactly match with a "wikipedia" definition, I don't give a shit.

you're using a term wrong then, according to WP and the current scientific and academic views.

2008-04-16 11:13

Martin Piper

Registered: Nov 2007
Posts: 647

Quote:
here's your definition wisey:

"In the context of this discussion the 6502 has two operating levels. One level is when it is executing an IRQ. The other not running an IRQ, we will call this the mainline."

as you cannot decide based on the I bit or whatever, wether cpu is executing an irq or not, you dont have two operating whatevers, as when two whatever cannot be told appart its the same whatever.

As shown it is possible to detect the state of the interrupt disable flag.

As I have already said it is completely irrelevant, for my point, to be able to detect if the interrupt disable flag is set from the result of an interrupt or as the result of SEI.

Just so you are clear, what you wrote does not matter and does not refute what I have been posting.

So, as defined in posts 80 and 85 and in the context of this topic there are therefore two operating levels.

2008-04-16 11:14

Martin Piper

Registered: Nov 2007
Posts: 647

Quote: you're using a term wrong then, according to WP and the current scientific and academic views.

You've not shown anything like that to be able to make such a claim.

2008-04-16 11:18

Oswald

Registered: Apr 2002
Posts: 5031

"In the context of this discussion the 6502 has two operating levels. One level is when it is executing an IRQ. The other not running an IRQ, we will call this the mainline."

read your definition again. how many times must I tell you the same thing? you cannot decide wether you are running irq or not, so u have no 2 op modes.

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