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Krill
Registered: Apr 2002
Posts: 2855 |
$D016 bit 5
There is this mysterious bit early on in the KERNAL reset routine:
FCEF: 8E 16 D0 STX $D016 ; VIC: Control Register 2 with X being anything in [0..5].
Now, some people [who?] claim that without this store to $d016, some [which?] cartridges won't start [citation needed].
However, $D016 apparently used to have a mysterious "reset bit" in supposedly early VIC-II revisions (those with only 5 not 9 luma steps, and then the early ones of those).
| Bit 5 | Reset-Bit: 1 = Stop VIC (no Video Out, no RAM |
| | refresh, no bus access) | Could this be the reason why some things on some machines (?) won't start without that store to $D016?
Do any machines still exist where setting $D016 to, say, $f8 would crash them (when running code from RAM)?
Or did this "reset bit" never exist? =) |
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chatGPZ
Registered: Dec 2001
Posts: 11148 |
Yes, that's it! |
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Martin Piper
Registered: Nov 2007
Posts: 646 |
In other words, from what I wrote earlier, "unexpected DRAM refresh signal timings" (RAS and CAS and the address lines) "flickering unexpectedly" causes "badly refreshed DRAM" aligns with the article "one memory cell gets refreshed with the bit value of a different memory cell". It is precisely to do with refresh of DRAM, or rather bad or faulty refresh in this case. |
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chatGPZ
Registered: Dec 2001
Posts: 11148 |
The DRAM refresh happens in the refresh cycles. There is no problem there.
You can write "incorrect" once more. |
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tlr
Registered: Sep 2003
Posts: 1727 |
Quoting KrillHowever, $D016 apparently used to have a mysterious "reset bit" in supposedly early VIC-II revisions (those with only 5 not 9 luma steps, and then the early ones of those).
The reset bit does not do anything on the 6569R1. I'm guessing early 6567's, maybe only prototypes even? |
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Martin Piper
Registered: Nov 2007
Posts: 646 |
Quote: The DRAM refresh happens in the refresh cycles. There is no problem there.
You can write "incorrect" once more.
From the article you cited: "In short, one memory cell **gets refreshed** with the bit value of a different memory cell."
It refutes what you claim and agrees with what I wrote "badly refreshed DRAM due to signals flickering unexpectedly".
How do you not understand that "one memory cell **gets refreshed** with the bit value of a different memory cell" is synonymous with "badly refreshed DRAM"? It's not like the DRAM is correctly refreshed, the signal are flickering basically changing unexpectedly, when they shouldn't be with relation to the RAS signal. |
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chatGPZ
Registered: Dec 2001
Posts: 11148 |
I understand exactly what your problem is, but i wont give another hint. It's ok. |
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Monte Carlos
Registered: Jun 2004
Posts: 351 |
Groepaz's bot active again ;-) |
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Martin Piper
Registered: Nov 2007
Posts: 646 |
Quote: I understand exactly what your problem is, but i wont give another hint. It's ok.
You fail to understand the article. That's what. |
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chatGPZ
Registered: Dec 2001
Posts: 11148 |
Your lack of knowledge and imagination to grasp factually accurate information about specific topics is appreciated. |
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Martin Piper
Registered: Nov 2007
Posts: 646 |
Quote: Your lack of knowledge and imagination to grasp factually accurate information about specific topics is appreciated.
The fact is you're wrong and you're refusing to admit it. |
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