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Silver Dream !
Registered: Nov 2005 Posts: 108 |
Large FLI picture
Greetings, exalted ones! I am looking for a large (not a narrow, logo type of) esteemed FLI picture with permission to reuse it in the BeamRacer programming tutorial example. Suggestions whom to turn to would be highly appreciated. |
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S.E.S.
Registered: Apr 2010 Posts: 19 |
I think so. But depending on the picture you want to display, instead of using a simple fixed round-robin method, you could each cycle update the register that contains the least useful color regarding the next 4 pixels. |
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Silver Dream !
Registered: Nov 2005 Posts: 108 |
Yes, you got it correct - one cannot address multiple VIC-II registers during single clock cycle. |
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Laurent
Registered: Apr 2004 Posts: 40 |
Quoting Silver Dream !Still, as FLI is based on increasing badlines frequency, it is probably not be the best example for huge savings. A badline is still a badline after all. Since beamracer is a "middle man" between VIC and the c64, isn't it able to drive AEC and BA on its own, overriding VIC's behavior ?
I believe the 6510 should not have to be stalled during badlines while beamracer's logic let VIC grab data from beamracer's local RAM. |
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Silver Dream !
Registered: Nov 2005 Posts: 108 |
New synthetic video modes, including "badlines-free" ones are in fact possible with BeamRacer. As is improving FLI to overcome the FLI-bug or add even more colours on its right-hand side. |
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soci
Registered: Sep 2003 Posts: 484 |
Is colour RAM shared for multiple FLI lines or that limit does not apply? (are all 12 data bits handled internally or are 4 of them pass through only?) |
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Silver Dream !
Registered: Nov 2005 Posts: 108 |
Quoting sociIs colour RAM shared for multiple FLI lines or that limit does not apply? (are all 12 data bits handled internally or are 4 of them pass through only?) Hi Soci! I am not sure if that's what you ask about but generally colour RAM remains static in FLI and the extra colours come from bank-switching screen matrix areas for each rasterline. But I bet this is something you surely know about and therefore you most probably ask about something else :-) Maybe you ask about overcoming the FLI-bug? Then also - colour RAM remains static (and still buggy) but the other two nibbles are programmable. |
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Laurent
Registered: Apr 2004 Posts: 40 |
yes the color ram remains static in FLI because the bus is constantly taken by the VIC to read char matrix bytes (badlines on every line), so the CPU or an external cartridge has no chance to do anything more.
But if beamracer's CPU is directly connected to the VIC data bus 8-11 for color ram, it is certainly able to give VIC a new "color ram color" each cycle, achieving better than FLI : three independent colors per 4x1 cell instead of two. |
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soci
Registered: Sep 2003 Posts: 484 |
It's not really clear how it operates from the documents.
So if I got it right there's bitmap sequencer which can replace bitmap data fetches with data from local memory.
But for the other half-cycle (e.g. video matrix access) now it seems it does no such tricks and just passes through everything without a change.
Earlier I thought it could replace those accesses as well and the question was if it's done 8 bits wide only or full 12 (that is including colour data). But now I think the question was wrong as no data replacement happens.
Edit: Originally I was thinking about something Laurent wrote just above. |
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Silver Dream !
Registered: Nov 2005 Posts: 108 |
I see - yes, Soci you got it right. The programmable sequencer can serve VIC's "g-accesses" and is a mother lode of new possibilities. It does not serve "c-accesses" though. Those are served the original way. |
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Silver Dream !
Registered: Nov 2005 Posts: 108 |
Quoting Laurentif beamracer's CPU is directly connected to the VIC data bus 8-11 for color ram, it is certainly able to give VIC a new "color ram color" each cycle, achieving better than FLI : three independent colors per 4x1 cell instead of two.
You are right, Laurent. In theory yes. In practice the "certainly" part is not entirely true due to several design constraints, including but not limited to the consciously introduced ones. |
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