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Monte Carlos
Registered: Jun 2004
Posts: 358 |
Left/Right Border switching in middle of rasterline
The last days i experimented a little with bit 3 of $d016. I had the brainfart to broaden the border on the left and keep it normal on the right. Disappointingly, this seems to work only in every non badline. If i try to switch bit 3 of $d016 during a badline i either get both left and right borders equal or i turn off the border completely for the next rasterline. Does somebody have an explanation in terms of internal VIC timing? I also tried modifying the timing with sprites or HSP to be able to write to $d016 in the correct cycle. |
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lft
Registered: Jul 2007
Posts: 369 |
Quoting Oswaldbtw why the fuck do anyone call that DMA ? its a total misuse of the term
It's correct usage of the term. DMA can also be in the direction from memory to peripheral (as in the case with the VIC accessing main memory without CPU involvement). I don't know why the definition you quoted says otherwise. |
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lft
Registered: Jul 2007
Posts: 369 |
Quoting Monte CarlosSo in cycle 55 DMA is still going on while in cycle 56 it's already over. That's why cpu can't access $d016 in cycle 55.
Perhaps one should try this with RamEx or SCPU?
No, DMA is going on until (including) cycle 54. But you can't write anything on the first available cycle, because that write is swallowed up during the three write-only cycles (normally 12-14).
All of this is described quite clearly in the vic article. |
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lft
Registered: Jul 2007
Posts: 369 |
Quoting Color BarMaybe you could postpone the badline condition until after the left border edge? Then you may be able to change $d016 in the left border and change it back again after it. Then force a badline condition.
Yes, that should work.
Quote:"Color Bar"]This will mess with the graphics on the badlines, I suppose. (If I understand it correctly, this is VSP, isn't it?).
It is VSP if the badline condition was triggered in idle mode. But you could also trigger it from display mode. For instance, you could use the "repeat row" trick to go from RC=7 to RC=0 without having a new badline. Then in the middle of that line, you can force a badline condition, which creates a partial FLI line (with the FLI bug somewhere in the middle of the line). |
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Oswald
Registered: Apr 2002
Posts: 5086 |
Quote: Quoting Oswaldbtw why the fuck do anyone call that DMA ? its a total misuse of the term
It's correct usage of the term. DMA can also be in the direction from memory to peripheral (as in the case with the VIC accessing main memory without CPU involvement). I don't know why the definition you quoted says otherwise.
its not correct usage, DMA is a technique to speed up I/O, esp. ment to ease up the CPU from the grunt work of copying bytes. The VICII is nor a peripheral, nor there's anything to speed up. Its wired into the system from day 0. There's no cpu job to speed up. There's no I/O. There's no peripheral.
DMA was invented after the c64 was released. How could it have DMA then ? But if you insist then we should call cpu mem accesses DMA too. Eventho it implies there's a no direct mem access too, which isnt there..
DMA stands for Direct Memory Access, a capability in modern computers that allows peripheral devices to send data to the motherboards memory without intervention from the CPU.
Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels |
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Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
Quoting lft
All of this is described quite clearly in the vic article.
Yes, but I'm afraid mastering it requires a lot of experimenting. |
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lft
Registered: Jul 2007
Posts: 369 |
Quoting Oswaldits not correct usage, DMA is a technique to speed up I/O, esp. ment to ease up the CPU from the grunt work of copying bytes.
The video interface controller is clearly an output device. (Actually, it's doing lightpen input too, but that part doesn't benefit from DMA.)
The fact that VIC reads memory directly does offer a performance advantage over solutions that involve the CPU, such as the VDC in the C128.
Quoting OswaldThe VICII is nor a peripheral
Neither is the VDC. But the VIC uses DMA and the VDC doesn't. Also, peripherals on the cartridge port have access to DMA using the exact same lines that VIC uses, and for the exact same purpose, with one exception: The peripherals also need to stay out of the way when the VIC needs the bus, because the VIC has highest DMA priority.
Quoting OswaldIts wired into the system from day 0. There's no cpu job to speed up.
There's no CPU job to speed up precisely because the VIC has direct access to the memory.
Quoting OswaldDMA was invented after the c64 was released.
That's incorrect. I don't know exactly when it was invented, but in this patent from 1978 for a shared DMA controller, we can read:
The concept of direct memory access is well known in the art. Generally speaking, this concept allows a central processing unit to load a subsystem device controller with the instructions and data necessary to initiate and carry out a data transfer between the memory and the peripheral device connected to and controlled by the subsystem device controller.
Quoting OswaldBut if you insist then we should call cpu mem accesses DMA too.
No, because the CPU would be involved during such accesses. |
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oziphantom
Registered: Oct 2014
Posts: 490 |
VSP puts you into 39x25 mode. |
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oziphantom
Registered: Oct 2014
Posts: 490 |
DMA is where something gets data from memory with out it being moved by the CPU. So the VIC grabs the data it wants we don't have to load the data into one of its registers for it to display data. Like you do on the 2600. The 128s VDC also has DMA but it gets the data from its VRAM. The VDC has a programmable DMA engine in that you can get the VDC to DMA copy data from one part of its VRAM to another. The VIC has fixed DMA.
The SID does not have DMA and to change music we must use the CPU to change the SID's registers. Paula has DMA so when she needs more sample data she will take over the bus and get her data from RAM. So the VIC,VDC DMA, the CIAs,SID don't DMA. |
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Flavioweb
Registered: Nov 2011
Posts: 463 |
I can't understand one thing:
how is possible to have left border opened and right closed?
If you open border at cycle 56, it "still open" since cycle 17 of next line.
If you set "CSEL=0 to CSEL=1 in cycle 17" border still open since next line cycle 17 (From Vic Aritcle: "Likewise the
horizontal border can be prevented from turning off by switching from CSEL=0 to CSEL=1 in cycle 17")...
Or i'm missing something? |
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tlr
Registered: Sep 2003
Posts: 1787 |
Quote: I can't understand one thing:
how is possible to have left border opened and right closed?
If you open border at cycle 56, it "still open" since cycle 17 of next line.
If you set "CSEL=0 to CSEL=1 in cycle 17" border still open since next line cycle 17 (From Vic Aritcle: "Likewise the
horizontal border can be prevented from turning off by switching from CSEL=0 to CSEL=1 in cycle 17")...
Or i'm missing something?
It isn't possible. The OP was about having a one char wider border on left side but normal width on the right. |
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