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Krill
Registered: Apr 2002
Posts: 2940 |
Shortest code for stable raster timer setup
While working on my ICC 2019 4K entry (now postponed to ICC 2020, but i hope it'll be worth the wait), i came up with this (14 bytes):initstabilise lda $d012
ldx #10 ; 2
- dex ; (10 * 5) + 4
bpl - ; 54
nop ; 2
eor $d012 - $ff,x; 5 = 63
bne initstabilise; 7 = 70
[...]; timer setupThe idea is to loop until the same current raster line is read at the very beginning (first cycle) and at the very end (last cycle) of a raster line, implying 0 cycles jitter.
With 63 cycles per line on PAL, the delay between the reads must be 63 cycles (and not 62), reading $d012 at cycle 0 and cycle 63 of a video frame's last line (311), which is one cycle longer due to the vertical retrace.
The downside is that effectively only one line per video frame is attempted, so the loop may take a few frames to terminate, and the worst case is somewhere just beyond 1 second.
The upside is that it always comes out at the same X raster position AND raster line (0), plus it leaves with accu = 0 and X = $ff, which can be economically re-used for further init code.
Now, is there an even shorter approach, or at least a same-size solution without the possibly-long wait drawback? |
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Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
Quote: Quoting Groepazrelying on anything being already initialized isnt really a good idea though. perhaps acceptable for something like a 4k - but for anything bigger i'd rather not do this. you can never know what some cartridge or kernal replacement does. Cartridge and KERNAL stuff do not play much of a role in demos, so it's not unusual to have timers for IRQ jitter compensation run during the entire multi-side demo without re-initialisation.
It's different for games, of course, but there you rarely need stable interrupts.
But then both multiload demos and games do not have much of a space issue, so just re-initialise timers at strategic/natural points and be done with it.
I did assume that $dc04 goes through all 256 values. If it runs at a period of 9 cycles, the SBX #51 will fail. If it runs at a period of 63 cycles, I don't know if it will work. That has to be analyzed. If it does, I expect that it often will take much longer to lock. Then again, as you point out, if it runs at these periods usually means that a raster syncing procedure has already been performed. |
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Krill
Registered: Apr 2002
Posts: 2940 |
Quoting Rastah BarI did assume that $dc04 goes through all 256 values. Note that by default, you cannot expect a timer period that is divisible by 256. That is, on timer underflow, the timer lo-byte will wrap to some other value than $ff. |
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Copyfault
Registered: Dec 2001
Posts: 468 |
The approach with the timer has some pitfalls but the idea behind it is really beautiful: to check if the timer has changed largely though the read-accesses to the timer-register are just a few cycles apart!
In some of my former posts I already wondered wether the timer underflow never misaligns the read values s.t. a badline might be detected while not being in one. And somehow it feels strange to use timers in a routine which aims to fix a raster cycle position s.t. a timer can be initialised in a stable way. Nontheless a valuable addition to the pool of (mostly insane) approaches :) |
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Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
Quote: Quoting Rastah BarI did assume that $dc04 goes through all 256 values. Note that by default, you cannot expect a timer period that is divisible by 256. That is, on timer underflow, the timer lo-byte will wrap to some other value than $ff.
Yes, but for the default ~60 Hz setting, that will only postpone locking somewhat. |
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Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
Quoting CopyfaultThe approach with the timer has some pitfalls but the idea behind it is really beautiful: to check if the timer has changed largely though the read-accesses to the timer-register are just a few cycles apart!
Thanks!
Quoting Copyfault
In some of my former posts I already wondered wether the timer underflow never misaligns the read values s.t. a badline might be detected while not being in one. And somehow it feels strange to use timers in a routine which aims to fix a raster cycle position s.t. a timer can be initialised in a stable way. Nontheless a valuable addition to the pool of (mostly insane) approaches :)
The default Kernal settings are such that a false positive cannot occur. But, as Groepaz pointed out, you can never know what some cartridge or kernal replacement does to the settings. |
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Krill
Registered: Apr 2002
Posts: 2940 |
Quoting Rastah BarThe default Kernal settings are such that a false positive cannot occur. But, as Groepaz pointed out, you can never know what some cartridge or kernal replacement does to the settings. This is the same hazard as relying on any kind of pre-initialised variable. Usually to be avoided, but okay for very tight size-restricted productions, such as 4K or smaller demos. =) |
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Copyfault
Registered: Dec 2001
Posts: 468 |
Quoting Rastah BarI checked all starting situations and if I did not make a mistake, the loop always ends! Can confirm :) Depending on the loop-cycle at raster-cycle#11 of, say, badline at $30, the loop-cycle-no. either rather quickly gets to 3 (and thus the S-cycle lands where it should), or the loop-cycle-no. gets into an "4/5<->11 endless cycle". No other endless cycles are possible.
So it suffices to check what happens when the loop-cycle at raster-cycle#11 of the last badline of the frame is 4/5 or 11. For this, see post#150. "QED", I'd say 8)=)
Quoting Rastah BarThe next exercise is to check this for C64 models other than PAL. Puhhh, not now, I'm just too happy it works for PAL :)
Quoting ChristopherJamQuoting Copyfault[...]Thanks for doing the analysis! Had to be done;) And I kinda like rastercycle-joggling... really sad it did not "pay off". And now it DID pay off :) I'm really happy now, 'cause we have just "proven" that
sta $d093,y
brk
with the brk replaced by any wanted value on the sync-loop's exit works!!! A 0-byte-sync-routine (ofcourse PLUS all the preparations, but those may serve other purposes, too). |
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ChristopherJam
Registered: Aug 2004
Posts: 1403 |
Victory! \:D/ \:D/ |
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Rastah Bar
Account closed
Registered: Oct 2012
Posts: 336 |
I checked NTSC1, NTSC2, and DREAN, but it doesn't work for these models. NTSC2 and DREAN have 65 cycles per line, and since this is a mutiple of the looplength of 13 cycles, the border changes nothing and won't get us out of an endless loop.
I found examples of endless loops for all models, and for NTSC1 the border does not save it either. So PAL only. |
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Copyfault
Registered: Dec 2001
Posts: 468 |
There's still some more to squeeze out of the "0-byte-approach", though one may argue that it becomes a 1-byte-routine this way...
Instead of changing the byte following the SHA (vec),y, we could change the low-byte of the BRK-vector. By doing so, the mem constraint of the routine (best fit was the $ffxx-page) can be lowered a bit:
*= page*$100 - 1
sta $d093,y
brk
Now init the BRK-vector with $00/#page, put #($fe-y)/$ff at $d0/$d1 and choose values for accu and x s.t. x&a=1 and the routine will still work (also widens the choice for a and x somewhat). |
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