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Forums > C64 Coding > Shortest code for stable raster timer setup
2020-01-20 16:20
Krill

Registered: Apr 2002
Posts: 2980
Shortest code for stable raster timer setup

While working on my ICC 2019 4K entry (now postponed to ICC 2020, but i hope it'll be worth the wait), i came up with this (14 bytes):
initstabilise   lda $d012
                ldx #10          ; 2
-               dex              ;   (10 * 5) + 4
                bpl -            ; 54
                nop              ; 2
                eor $d012 - $ff,x; 5 = 63
                bne initstabilise; 7 = 70

                [...]; timer setup
The idea is to loop until the same current raster line is read at the very beginning (first cycle) and at the very end (last cycle) of a raster line, implying 0 cycles jitter.

With 63 cycles per line on PAL, the delay between the reads must be 63 cycles (and not 62), reading $d012 at cycle 0 and cycle 63 of a video frame's last line (311), which is one cycle longer due to the vertical retrace.

The downside is that effectively only one line per video frame is attempted, so the loop may take a few frames to terminate, and the worst case is somewhere just beyond 1 second.

The upside is that it always comes out at the same X raster position AND raster line (0), plus it leaves with accu = 0 and X = $ff, which can be economically re-used for further init code.

Now, is there an even shorter approach, or at least a same-size solution without the possibly-long wait drawback?
 
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2021-01-30 21:27
Krill

Registered: Apr 2002
Posts: 2980
No worries, i actually took it for a mistake.

Though i wonder how that could happen, did you drunkenly type in some notes scribbled on a napkin, mistaking an A for a 4? =)
2021-01-31 00:42
Raistlin

Registered: Mar 2007
Posts: 680
So you're suggesting there was a fault in Copyfault's copy?
2021-01-31 00:51
Copyfault

Registered: Dec 2001
Posts: 478
Quoting Raistlin
So you're suggesting there was a fault in Copyfault's copy?
Yeah, must be the handle, obviously ;)
2021-01-31 10:24
Oswald

Registered: Apr 2002
Posts: 5094
0843 A2 9E LDX #$9E
0845 A0 08 LDY #$08
0847 E0 00 CPX #$00
0849 D0 F9 BNE $0844

could someone explain how this works ? :D
2021-01-31 11:34
Krill

Registered: Apr 2002
Posts: 2980
Quoting Oswald
0843 A2 9E LDX #$9E
0845 A0 08 LDY #$08
0847 E0 00 CPX #$00
0849 D0 F9 BNE $0844

could someone explain how this works ? :D
Corrected version of the code and Copyfault's explanation annotated:
08A3 A2 9E   LDX #$9E
08A5 A0 08   LDY #$08
08A7 E0 00   CPX #$00
08A9 D0 F9   BNE $08A4
Branching to $08A4 leads to SHX $08A0,Y with Y = 8, so the operand byte of the CPX #imm at $08A8 is altered continuously.
As long as the "&(hi+1)" plays in, the CPX #imm operand will be $9E & $09 = $08, which is not equal X = $9E, so branching back.
When "&(hi+1)" disappears, the full $9E is written to the CPX's operand byte and the loop will end (X = $9E with CPX #$9E will yield Z=1). This happens if and only if the critical SHX-cycle appears on a badline.
2021-01-31 12:35
Oswald

Registered: Apr 2002
Posts: 5094
why does the &hi disappear on a badline?
2021-01-31 12:39
chatGPZ

Registered: Dec 2001
Posts: 11386
thats what the opcode does - why exactly it happens is unknown, but its likely some analog effect
2021-01-31 13:21
Krill

Registered: Apr 2002
Posts: 2980
Yes, something to do with DMA interference* disturbing the inner workings of that opcode. And it's a non-intended (illegal) opcode anyways, so short-circuiting inner logic to begin with. :)

* It has been observed that other 6502-based platforms without DMA (1541, e.g.) do not exhibit the &H-dropoff behaviour.
2021-01-31 15:04
Copyfault

Registered: Dec 2001
Posts: 478
Quoting Oswald
why does the &hi disappear on a badline?
In my text "badline" was short for "the 1st DMA-overtake-cycle @cycle#12 in every badline".

If the 4th cycle of the SHX abs,Y coincides with a DMA-overtake cycle, the &(hi+1) drops off, see e.g. post#88 or the latest No More Secrets V0.95.

Ofcourse all sprites must be turned off while the routine is running (they'd throw in other DMA-overtake-cycles and break the whole thing). So the basic trick (courtesy of Quiss;)) is to uniquely mark badlines with the DMA-overtake-cycles and loop until the beforementioned 4th cycle of the SHX lands on the correct cycle (or short: "on a badline";)).
2021-02-01 00:44
Devia

Registered: Oct 2004
Posts: 401
What an awful thread.. fell down the rabbit hole, turned utterly insane, lost several days of sleep...
Quiss' original approach is short and elegant, but opcode rewriting confuses my old brain.
Adding a single byte to it's size, the flexibility can be increased somewhat (from 64 to 112 possible pages) and no opcode rewrites, just operand rewrite.

	* = $xy00, where x=$0-$f and y=$0-$6
loop:	ldy	#$08
	ldx	#$0a
	shx	loop,y
	jmp	loop
$xx0A:

Loop times kept at either 10 or 12 cycles, depending on address choice.

As an added bonus, A is not touched - which may or may not matter in your overall timer setup.

So, it's obvious my priority is not size, but readability - and I find this approach a tad more readable ;-)
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