| |
chatGPZ
Registered: Dec 2001
Posts: 11386 |
(Ab)use of dummy accesses
For the next release of my "No more Secrets" doc i am preparing a chapter related to the dummy access which happen when the CPU performs an internal operation. Once again i am looking for some examples on how to (ab)use it :) I guess everyone knows "inc $d019" - but i am sure there is more than this. And not only with RMW instructions. So if you have anything in your mind - just drop it here!
here are some related notes which i pasted together. feel free to proofread and point out mistakes :) |
|
| |
JackAsser
Registered: Jun 2002
Posts: 2014 |
Lovely stuff!!!
” Most 1-Byte instructions will fetch PC+1 after the opcode fetch”
All 1-byte right? |
| |
Fred
Registered: Feb 2003
Posts: 285 |
A good example of the usage of fetch next opcode (NewPC) is to acknowledge NMI after executing the RTI instruction:
JMP $DD0C
;DD0C 40 RTI
This will execute the RTI instruction at $DD0C but since it will also read the next opcode, it will perform a read at $DD0D which will acknowledge the NMI.
Some music routines (like the 8bit digi routine from THCM) make use of this to win some cycles to end the NMI routine. |
| |
Fred
Registered: Feb 2003
Posts: 285 |
The music routine from Fred Gray performs a read and write on IO with:
LDA #$40
STA $D404
INC $D404
Which will toggle the gate bit of the control register of the SID chip. |
| |
chatGPZ
Registered: Dec 2001
Posts: 11386 |
JA: yeah, dunno why i wrote "some" :) (the byte after opcode will simply be fetched always)
Fred: ok, this saves one cycle :) |
| |
Fred
Registered: Feb 2003
Posts: 285 |
Another usage of a dummy read cycle is the following code:
LDX #$F0
LDA $DC1D,x
This will do a dummy read at $DC0D and a normal read at $DD0D. With this way you can acknowledge both CIA timers in one instruction.
The way it works is that the CPU will first read the address without correcting the high byte in cycle T3:
T0 Fetch opcode
T1 Fetch low order byte of Base Address
T2 Fetch high order byte of Base Address
T3 Fetch data (no page crossing)
T4 Fetch data from next page
T0 Next Instruction
and then it fetches the data from the next page at cycle T4. |
| |
Copyfault
Registered: Dec 2001
Posts: 478 |
Feeding data to the sprite pattern pipe for a sprite that is displayed "far out right" which did not have its DMA-cycles before comes to mind.
IIRC, the only way to get all three pattern bytes filled correctly you needed aSTA VIC_REG,x at the correct position in the rasterline, s.t. the 4th cycle occurs at the first sprite DMA-cycle and the 5th (the W-cycle) at the 2nd sprite DMA-cycle. This way, the sprite pattern byte was filled with byte read in 4th cycle from the (uncorrected!) VIC-adress | ghostbyte | byte stored in 5th cycle , so the internal operation cycle was mandatory to achieve this. |
| |
Compyx
Registered: Jan 2005
Posts: 631 |
Copyfault: are you talking about the 'x-stretch' effect you get with dysp's when the low-index sprites go too far into the right border? |
| |
chatGPZ
Registered: Dec 2001
Posts: 11386 |
Quote:The music routine from Fred Gray performs a read and write on IO
thats not abusing the dummy accesses though.... it relies on the floating bus value (what a terrible idea =P) |
| |
tlr
Registered: Sep 2003
Posts: 1790 |
Quote: Copyfault: are you talking about the 'x-stretch' effect you get with dysp's when the low-index sprites go too far into the right border?
It refers to the long mysterious $ff glitches usually appearing at the top of sprite #0 when moved far right (it appears for all sprites but most not visible). Those can be controlled by placing the right values on the internal vic-bus in two adjacent cycles.
There's a length discussion in a thread somewhere. |
| |
chatGPZ
Registered: Dec 2001
Posts: 11386 |
it would be great if you'd post an actual working example, that would safe a lot of time =) |
... 55 posts hidden. Click here to view all posts....
|
| Previous - 1 | 2 | 3 | 4 | 5 | 6 | 7 - Next |
