VIA timers are only 16bit and can not be cascaded [...] Bonus question: can we use https://en.wikipedia.org/wiki/Chinese_remainder_theorem with two VIA timers to make this more accurate? or is it a pointless exercise?
; timers/watchdog initialisation ; for the long timeout between block-ready and block-send, use two arithmetically cascaded timers: ; their periods differ, so their counters drift further apart every time either timer resets. ; the effective timeout is reached as soon as the difference between the counters is >= 128, which for ; the used periods' difference of 7 cycles with the counter periods of $ef00 and $ef07 is at least ; floor(128 / 7) * $ef07 = 18 * $ef07 = 1,101,438 cycles at 1 MHz, i.e., roughly 1 second. ; a few cycles are added to or subtracted from the effective timeout: added because as a counter reset ; apparently takes 2 cycles, so the effective periods are $ef02 and $ef09, subtracted because the counters' ; difference does not increase by 7 on counter $ef07 reset, but increases by 7 and then decreases by 2.
Bonus question: can we use https://en.wikipedia.org/wiki/Chinese_remainder_theorem with two VIA timers to make this more accurate? or is it a pointless exercise?
Note, don't put in vice repository a "derived" test (i.e. copied). Just put my program.
Another note: it's totally useless to use both VIA timers. Considering the speed range of VICE, the difference between 275 RPM and 325 is 33566.4 cycles which is fine because it's smaller than the 65536 cycles the timer can give us.
The question still is: by doing that, do we gain accurracy over the free running timer? Like Zibri said, we know already we will measure something close to 200000 cycles, and we dont have to be able to measure arbitrary times.
Z_M X Z_N -> Z_N; (m, n) |-> n-m