| |
chatGPZ
Registered: Dec 2001
Posts: 11386 |
(Ab)use of dummy accesses
For the next release of my "No more Secrets" doc i am preparing a chapter related to the dummy access which happen when the CPU performs an internal operation. Once again i am looking for some examples on how to (ab)use it :) I guess everyone knows "inc $d019" - but i am sure there is more than this. And not only with RMW instructions. So if you have anything in your mind - just drop it here!
here are some related notes which i pasted together. feel free to proofread and point out mistakes :) |
|
... 55 posts hidden. Click here to view all posts....
|
| |
Fred
Registered: Feb 2003
Posts: 285 |
Quote: Oh, damn. Thanks for that, Fred.
I guess you could safely write 0 then 1 if you first wrote a zero to some other SID register before INC $d404, but this is all sounding a bit flaky now :)
That's why the music routine of Fred Gray first writes to $D404 and then immediately increases it to toggle the gate bit like:
STA $D404
INC $D404 |
| |
CyberBrain
Administrator
Posts: 392 |
Quote: That's why the music routine of Fred Gray first writes to $D404 and then immediately increases it to toggle the gate bit like:
STA $D404
INC $D404
I wouldn't say so, since that snippet writes to the same register that it addresses with the INC afterwards, which doesn't really abuse the dummy-write.
In the snippet, the INC dummy-write just writes whatever was already there, which to my knowledge doesn't cause any side effect for $D404. (Am i wrong?)
But according to the resid-fp documentation, an INC doesn't necessarily have to set the register to the same value that the register already had in its first write cycle.
It can set the register to any value V you want in the first write cycle, and then set the register to V+1 one cycle later (at the second write cycle).
This could for example be used to toggle the gate and then toggle it again the next cycle. (Not sure if that's useful)
// Example - assume the gate-bit is 1 here
lda #%xxxxxxx0 // <- Select whatever waveform, etc, bits you want here, but keep bit 0 zero.
sta $D4xx // <- Some SID-register we don't use and is not audible (pulse-width for example)
inc $D404 // <- Cycle 5: set gate=0. Cycle 6: set gate=1.
Normally the minimum delay between toggling would be 4 cycles. Same could be done for any other write-only SID register (+ with ROL/ROR/ASL/LSR).
I wonder how reliable it is reading the write-only registers - it sounds like it is pretty reliable when done within "a few cycles" judging from the wording from resid-fp. |
| |
chatGPZ
Registered: Dec 2001
Posts: 11386 |
its pretty reliable even with a surprising number of cycles gap... see the "bitfade" tests :) |
| |
CyberBrain
Administrator
Posts: 392 |
Really interesting! There must be some use-case for this (perhaps controlling the internal counters as ChristopherJam mentioned)
An update to the example i posted: Since reading a write-only register returns the last written value to ANY register (not just to write-only registers), you don't even have to trash the value of a register for this trick to work. Just write to one of the read-only registers. |
| |
chatGPZ
Registered: Dec 2001
Posts: 11386 |
Also a good way to show the finger to shitty replacements =P |
| |
Frantic
Registered: Mar 2003
Posts: 1648 |
Quote: Also a good way to show the finger to shitty replacements =P
Ah.. yes! I'll remember that! :) |
| |
Compyx
Registered: Jan 2005
Posts: 631 |
Quoting tlrAre we counting things like inc $d016;dec $d016 in this btw? More related to BA i guess but if there weren't so many dummy cycles it wouldn't work.
I wouldn't count that under the dummy writes/reads. You're just wasting cycles with a RMW instruction to inhibit sprite 0 DMA screwing with opening the border. |
| |
ChristopherJam
Registered: Aug 2004
Posts: 1409 |
Quoting ChristopherJamI'm fairly sure one of the iterations in developing a stable hard restart used one cycle blips of the gate bit to allow RC to escape at known times, but it didn't turn out to be the most optimal. I'll have a rummage.
"sieve" at SID envelope rate counter phase alignment - which just reminds me I need to fix the hosting of those images and runlogs..
But yes, interesting that the readback is perfectly reliable if you're safely under 2000 cycles. Presumably one could first write to one of the undefined registers between $1d and $1f to much the same effect. |
| |
chatGPZ
Registered: Dec 2001
Posts: 11386 |
Hey, is that all? *push* :) |
| |
S.E.S.
Registered: Apr 2010
Posts: 19 |
If you want to have raster splits that are exactly 5 cycles wide, you can use ldx #$ff
ldy #$05
lda #$00
sty $d021
sta $cf22,x I don't know if anybody actually used that in an intro or a demo, though :) |
| Previous - 1 | 2 | 3 | 4 | 5 | 6 | 7 - Next |
